Abstract: A chip scale package (CSP) is disclosed. The CSP includes a die with bonding pads at the two lateral sides of active surface. A plurality of leads are adhered on the die, each lead has a first end, a second end. A plurality of metal bonding wires electrically connect the first ends of the leads with the die, and a first sealing layer covers the active surface of the die and the metal bonding wires. Each lead also has a protruding portion over the first sealing layer and located between the first end and the second end for outer electrical connection. Thus, the CSP has a smaller surface mounting area.