Abstract: A process and circuit for measuring the jitter modulation of a digital signal in which first pulses, which are derived from certain pulse flanks of the jitter-associated digital signal, and second pulses of a jitterfree reference clock pulse, which are derived from the bit repetition frequency of the jitter-associated digital signal, are subjected to a phase comparison. A reference clock pulse is generated with a pulse-repetition frequency nf.sub.B =f.sub.T corresponding to a multiple n of the bit repetition frequency f.sub.B of the digital signal and each bit period with a duration T.sub.B =1/nf.sub.B is divided into n partial periods each having a duration t=T.sub.B /n=1/nf.sub.B. The ramp generator (5) is started upon the application of a release signal once in each bit clock period p partial periods after the end of that partial period in which appears the predetermined pulse flank of the digital signal (DS), where p=0, 1, 2, . . . <n.