Abstract: A photodiode having an antireflection coating for use in optical measuring devices has its antireflection coating so selected that it provides in a predetermined wavelength range an approximately constant conversion factor. The conversion of the fight power to an electrical signal is thus substantially independent of wavelength over this wavelength range.

Abstract: A method for data or measured value averaging and compression for measuring instruments, particularly for spectral analyzers, in which in successive measuring runs with respect to measuring intervals minimum and maximum values and their precise position are determined and used for averaging taking account of the values determined at the same locations during further measuring runs. By means of a measured value or data determination dependent on the position of the fixed minimum and maximum values, it is ensured that an effective noise averaging and a reliable detection of narrow pulses are made possible.

Abstract: An adaptor (1) can be releasably connected to a fixed plug portion (13 or 21). The fixed plug portion is, with that, for example a component in a measuring device for taking measurements on differing optical fibers. The adaptor is provided with a sleeve (3) in which various transferable plug portions can be temporarily inserted. The sleeve has an axially parallel slot (6) for accommodating a rotational security device on an initial category of fixed plug portions (21). Additionally, the sleeve also has at least one further recess (4, 4, 5) on its outer casing for accommodation of the rotational security device (19, 19', 20) of a second category of fixed plug portions (13). In this way, an interface between adaptor (1) and fixed plug portion (13, 21) is created, which indeed enables combination with an adaptor equipped in the same way, although an adaptor without an additional recess is only able to be placed on one of the two categories.

Abstract: A method of and a circuit arrangement for detecting synchronization of two word sequences between a measurement signal and a reference signal. The signals are applied to an exclusive OR-gate comparator whose output produces an error signal which is compared with an error signal shifted by one period. This comparison is effected by an exclusive OR-gate and in the case of coincidence, indicating that the measurement and reference signals are phase-shifted, a new synchronization is enabled. The output of the exclusive OR-gate is an error signal which is time-shifted in a shift register and multiplexer so that the time shifted bit sequence is compared with the bit sequence of the first error signal in a second exclusive OR-gate which is connected to an AND-gate for detecting coincidence and generating a further synchronization signal which is processed through counters, another AND-gate and a flip-flop to produce the synchronization signal which is applied to the reference pattern generated.

Abstract: An adjustable impedance-correcting delay line adapted to form a standard line for providing an adjustable group delay time for measurement purposes or the like in which a plurality of different delay networks including coaxial segments of different lengths with or without damping compensating amplifiers can be selectively connected in the cascade or shunted. A bridge circuit can be provided with fundamental damping and delay time for bridging with the standard delay line where difference measurements are of interest.

Abstract: An optical plug connector for an optical measuring device between an internal light waveguide optical fiber and an external light waveguide optical fiber maintains a distance d between the ends of the fibers which is greater than the coherence length of the light to be transmitted through the coupling. In this manner, in spite of the presence of the air gap, interference phenomena are avoided.

Abstract: A method of and a circuit for detecting a cell loss and/or a cell insertion in cell structured signals traversing a cell oriented transmission module. A bit comparison is effected between a test signal sequence formed as a cell header and an information signal sequence filling the remainder of the cell and the bit comparison can detect the leading or lagging by a bit. When this bit comparison is, in addition, continuous; a cell loss or cell insertion is determined.

Abstract: An electronic measuring instrument capable of receiving control signals for setting same, is set by a bar-code reader through an encoder and processor utilizing setting instructions printed in bar-code form, so that the instruction set is accurately transferred to the microprocessor generating the control signals.

Abstract: A frequency divider circuit, especially for use in frequency synthesizers, in which the frequency divider is provided with whole-number division factors, permits intergrator, differentiator and/or phase accumulations to be used to generate the successive values of the division factor which average, over time to allow fractional frequency division.

Abstract: An optical head having a photoelectric converter at one end and a socket for a light guide plug at the opposite end, has a spring loaded apertured diaphragm adapted to press lightly against the front end of the plug when it is inserted into the socket. The diaphragm has a cylindrical aperture at its side turned toward the plug and an opening defined by a frustoconical surface widening in the direction of the converter. This surface and the rear wall of the diaphragm can be provided with a light absorbent coating or the surface can be reflective and the rear wall provided with a light absorbent coating.

Abstract: A dc converter for supplying an electronic device in which a feed voltage is summed with an additional voltage generated by rectification and wherein pulse-width control is provided at the primary side of the converter transformer. According to the invention, the additional voltage is generated by rectification in the same manner as the main output voltage is generated, i.e. the rectifier circuit outputting the additional voltage is similar to that outputting the output voltage.

Abstract: For imitating periodic signals occurring in digital transmission systems during some operating conditions in view of the multiplex structure a word generator is proposed which includes a read-only memory from which during a test signal cycle only 4116 permutations are successively read out of a total of 65,536 possible word sizes and permutations of e.g. a 16-bit word. The remaining 61,420 permutations are generated by shifting bit-by-bit the entire packet of continuous signals so that in case of a fixed 16 bit pattern the packet starts at a different bit position during each successive cycle and after 16 cycles all 16 bit positions occur as begin state. The shift is caused by a framing bit sequence which determines the test signal cycle and whose length is aliquant to n=16.

Abstract: A variable-frequency main oscillator of digitally tunable high output frequency f.sub.A is controlled by the integrated output voltage of a phase discriminator receiving on the one hand a relatively low comparison frequency and on the other hand a matching feedback frequency stepped down from output frequency f.sub.A by frequency division or by heterodyning with an auxiliary frequency f.sub.H of the same order of magnitude from an ancillary oscillator, a difference frequency f.sub.D =f.sub.A -f.sub.H is fed to a frequency discriminator delivering a corrective voltage, independent of that emitted by the phase discriminator through a filter network, to the control input of the main oscillator. A pair of frequency selectors varying the feedback frequency and/or the comparison frequency enable the output frequency f.sub.A to be adjusted in coarse and fine tuning steps, the coarse adjustments being also applied to the auxiliary frequency f.sub.H to limit the excursions of the difference frequency f.sub.D.

Abstract: In order to evaluate the fidelity of a transmission line or other test object, a pseudorandom bit pattern is fed to the input end of that test object and is compared bit by bit with the pattern exiting at its output end. Since independent transmission errors are considered particularly relevant for this evaluation, in contrast to consequential errors following an initial error within a predetermined number of bit cycles, an error pulse emitted by the bit comparator causes the blocking of further error pulses for a selected time interval. The blocking may be effected by a retriggerable monoflop of adjustable off-normal period or by a presettable down counter.

Abstract: In order to extract from a digital signal a train of sync pulses faithfully reproducing any phase jitter to which that signal is subjected, a pulse generator with a cadence equal to the reciprocal of the mean bit period is interrupted and restarted by a pulse shaper such as a monoflop in response to each incoming "1" bit. The pulse generator may comprise a second monoflop, triggerable by the first monoflop and provided with a feedback loop including a third monoflop which is inhibited by the first one in the presence of a "1" bit, or a free-running oscillator working into a frequency divider in the form of a pulse counter which is reset by the pulse shaper while the latter inhibits the oscillator.

Abstract: An incoming a-c signal, whose amplitude is to be measured, successively passes through several decadic attenuator stages settable by respective cascaded decadic stages of a reversible counter. The attenuated signal is rectified and its voltage, or the RMS value thereof obtained from a squarer, gives rise to a calibration current, opposed by a constant reference current, for charging a capacitor of a current/frequency converter with a resulting current corresponding to their difference. Two threshold detectors in that converter, responding to a capacitor charge of either polarity beyond a predetermined limit, trigger a monoflop which fully or partly discharges the capacitor and steps the counter forward or backward as determined by a polarity sensor connected across the capacitor. A retriggerable second monoflop, responsive to the trailing edge of each stepping pulse, enables the second-lowest counter stage to be stepped out of turn when these pulses follow one another at high rate.

Abstract: A four-terminal network selectively convertible into a low-pass, high-pass, band-pass, all-pass or band-stop filter comprises three cascaded stages each including an operational amplifier with a grounded noninverting input, the amplifiers of the first two stages being of the integrating type provided with capacitive feedback circuits. Resistive feedback connections extend from a main output A of the third stage to the inverting inputs of the first and third stages and from a relatively inverted output A' of the third stage to the inverting input of the second stage, their respective resistances R.sub.u, R.sub.v, R.sub.w determining the coefficients of the denominator in a biquadratic equation ##EQU1## where H(p) is the transfer function of the network and p=jf/f.sub.n is given by the ratio of an operating frequency f to a reference frequency f.sub.o. The coefficients of the numerator, which could be of either sign and may also be zero, are determined by supply resistances R.sub.a, R.sub.b, R.sub.