Abstract: In a generator whose frequency can be set digitally and connected in a phase-locked loop (PLL) with a frequency divider whose frequency divider ratio is periodically changed, the sum of the phase errors, which are the phase deviations of the individual frequency-divider delivered pulses from the phase of the reference frequency, is calculated and each pulse for which the phase-error sum exceeds a predetermined value is delayed by a time period corresponding to this value before being fed to the phase meter or phase detector of the phase-locked loop. As a result, any drift or oscillatory fluctuations of the voltage-controlled oscillator (VCO) control voltage are confined to substantially high frequencies and only very weak subharmonic components, and the oscillatory fluctuations can be filtered out easily by a low-pass filter between the phase detector or phase meter and the control-voltage input of the VCO.

Abstract: A plurality of first stations are linked with respective connectors which can be selectively activated to establish a signal path between any one of these stations and a second station via an intervening coupling network. Each connector includes at least one series switch between a pair of shunt switches, the former being closed while the latter are open in the activated state thereof. Selection is carried out with the aid of a control unit which, upon a switchover from one first station to another, sends a test signal through the hitherto active connector with successive reversals of its shunt and series switches and with measurement of the resulting impedances of that connector to determine its decoupling effect before activating the newly selected connector.

Abstract: A frequency generator of the digitally settable type comprises several voltage-controlled oscillators, specifically a pair of pilot oscillators and a final oscillator, provided with respective phase-locking loops each including a phase discriminator. The loops of the pilot oscillators further include respective frequency dividers whose step-down ratios are controlled by setting commands stored in associated memories which can be reloaded, under the control of manually or automatically adjustable selectors, only in the presence of an enabling pulse generated by a coincidence circuit with inputs connected to the outputs of a source of reference frequency and of the several stages of a chain of binary dividers connected to that source, certain of these stage outputs delivering comparison frequencies to the phase discriminators fed by the frequency dividers of the pilot oscillators.

Abstract: The average amplitude of an incoming signal voltage of variable frequency is measured by half-wave rectification of that signal voltage to produce a pulsating current which is subtracted from a continuous current in the input of an integrating amplifier. The fluctuating output voltage of this amplifier is periodically sampled, once per cycle of the signal voltage, to provide a train of corrective pulses. These pulses are accumulated to provide a reference voltage fed to a differential amplifier which controls the continuous current in response to differences between this reference voltage and a feedback voltage proportional to that current to compensate for changes in average signal amplitude. The magnitude of the continuous current, read by a meter, is therefore a measure of the desired amplitude. The voltage samples may be weighted, in proportion to signal frequency, by a variable-gain amplifier or a sampling switch closed for different periods in the output of the integrating amplifier referred to.

Abstract: Bipolar signals used in binary or ternary data transmission, arriving at a receiving station, are periodically sampled under the control of sync pulses extracted from the incoming data train. The samples are rectified and stored on a capacitor whose voltage variations, upon rectification and integration, yield an indication of signal distortion during transmission. The average capacitor charge furnishes a feedback signal for keeping the voltage variations proportional to signal amplitude. A threshold circuit prevents the sampling of zero or near-zero voltages with ternary signaling.

Abstract: A digitally settable frequency generator comprises a master oscillator whose operating frequency f.sub.Q is variable between a normal value f.sub.Q " and a slightly lower value f.sub.Q ' = (1-p)f.sub.Q " with the aid of a normally disconnected tuning capacitor. The master oscillator works into a frequency divider of fixed step-down ratio m:1 (or 2m:1) to produce a reference frequency f.sub.B. A slave oscillator, generating an output frequency f.sub.A = gf.sub.B, is controlled by a phase-locking loop including a phase comparator to which the reference frequency f.sub.B is fed along with a like frequency obtained from output frequency f.sub.A with the aid of another divider having a digitally variable integral step-down ratio g:1. A fractional value i, which may range from 0 to 100%, is set with the aid of a numerical interpolation selector to determine the number n<m of cycles of operating frequency f.sub.Q within a cycle (or half-cycle) of reference frequency f.sub.

Abstract: Two (or more) periodically reproducible input signals V.sub.yI, V.sub.yII, possibly including a constant reference signal, are visually displayed on an oscilloscope screen with the aid of a normally suppressed electron beam under the control of a horizontal-sweep generator and a vertical-sweep generator producing a sinusoidal x-deflection and y-deflection signals V.sub.xR and V.sub.yR, respectively. The x-deflection signal V.sub.xR is continuously compared with two (or more) ramp signals V.sub.xI and V.sub.xII, of different periodicities substantially lower than the frequencies of the deflection signals, respectively assigned to the input signals V.sub.yI, V.sub.yII to be displayed; upon the occurrence of a coincidence with one of these ramp signals, the horizontal sweep is halted or slowed down -- preferably to the slope of the coincident ramp signal -- for a display interval equaling one cycle of the y-deflection signal V.sub.

Abstract: To check the bit-distortion ratio of a transmission line carrying bipolar PCM signals, converted from a binary to a balanced ternary code at the tramsmitting end and reconverted into binary signals at the receiving end, binary test words and identical reference words are simultaneously read out from storage at opposite ends of the line. The test words are converted into bipolar form, for transmission, and the received pulses are distributed according to polarity over a first pair of leads while the binary pulses of the reference words are distributed over a second pair of leads according to the conversion code used at the transmitting end. The pulse trains on corresponding leads are compared, bit by bit, in a deviation monitor whose output, in response to any mismatch, advances a reversible counter which is reverse-stepped by timing pulses of a cadence reduced by a frequency divider to a fraction of the bit rate.