Abstract: A videotex decoder apparatus which, in various aspects, displays a status line to indicate when connect charges are occurring; overlays menus over displayed videotex frames with portions of the displayed frames remaining visible; provides easily called log-on procedures; retrieves remote information frames by user-specified keywords names; prints information frames in selectable different overall sizes; provides selectable different character sets for display; is table-driven; is structured to include a device independent decoder and device dependent drivers; includes a controller which feeds bytes to the decoder for decoding without regard to the protocol-dependent information content of those bytes; and uses an added frame header on stored frames to indicate the videotex protocol for decoding the frames.

Abstract: A clamp holds a sleeve over an installed connector preventing access to the connector for removal. The clamp is clamped to a cable with a screw having a head that breaks off after installation.

Abstract: Apparatus for removably attaching display apparatus such as an LCD screen to electrical apparatus. The attachment apparatus provides for electrical and mechanical attachment and detachment of the display apparatus in a single operation. When the display apparatus is detached, the attachment apparatus also provides for attachment of different display apparatus to the electrical apparatus. The attachment apparatus consists of a socket including a male electrical connector and a plug including a female electrical connector. When the plug is inserted into the socket, the male and female electrical connectors are connected, thereby providing power and signals to the display apparatus. The plug is held in the socket by means of a lever-actuated friction mechanism.

Abstract: A flexing connector for suppressing electromagnetic radiation from an electrical cable connecting moving and stationary elements of a machine has a shield surrounding a signal cable which includes an inner coil of wire wound in a generally helicoidal form with a flat cross-section with the signal cable positioned within the coil. An outer coil similar to the first, but with somewhat larger cross-section and wound with a different chirality, surrounds the inner coil. The coils are made from hardened steel, which is both electrically conductive and ferromagnetic. The two coils and the cable are clamped together on either side of a moving loop extending between the moving and stationary elements so that the coils cannot elongate and spread their windings apart as the connector is flexed.

Abstract: Apparatus and method for reconfiguring a memory in a data processing system to increase the rate of information transfer between system memory and processor. The system memory is comprised of a plurality M of memory banks, each having a separate data output path. In a first configuration a memory controller addresses the memory banks sequentially to read from one address location at a time. The memory is reconfigured by an address translator providing addresses addressing M banks in parallel, so that M locations are read in each read operation, and a bus reconfiguration multiplexer which reconfigures the bank output busses in parallel and selects one or more bank output busses as the memory output to the system processor.

Abstract: Apparatus for temporarily attaching one object to another object which includes a channel on one object, a form on the other object which may be slidably inserted into the channel, a flap on one object, and means for engaging the flap on the other object. The objects are connected to each other by sliding the form into the channel and then engaging the flap with the engagement means when engaged, the flap prevents sliding motion, and thereby ensures that the form does not slid out of the channel.

Abstract: A system for converting an input bitmap image of one resolution to an output bitmap image of a different resolution. A mapping is defined between pixels in the input bitmap and pixels in the output bitmap. An error term is used to link successive output pixel determinations. For each output value determination, the values of the mapped input pixels are added to the error term to create a test value that determines what output is generated; the output value generated therefrom is then subtracted from the test value to create the next value of the error term. The conversion system is of particular advantage in converting an image having gray scale that is represented in a binary bitmap where gray scale is represented by the ratio of the number of "on" pixels to the number of "off" pixels. The present image conversion system performs a conversion such that the output bitmap represents such gray scale particularly well.

Abstract: A modularly expandable keyboard has expansion modules which are integrated into an elementary keyboard by locking tongues inserted in depressed tracks in the modules and held in place by detents in the attached modules. The detent mechanisms are formed integrally with the housings of the modules and are unstressed when fully engaged. An electrical interconnect plug integrates the electrical busses of attached modules. Modules can be attached to either right or left and additional modules can be attached to already attached modules indefinitely.

Abstract: A tunable operating system in a multiprogrammed data processing system prevents lockout of I/O bound tasks of low priority by CPU bound tasks of high priority. A range signal in the master control block and a range divider signal in each task control block together define a queue subset for each task. The queue subsets for different tasks are overlapped by at least one queue, and preferably by at least three queues. A plurality of time-slice values, preferably two, are assigned when tasks are dispatched; the time-slice values are assigned with respect to the task range divider signal and therefore are not fixed with respect to each queue. The invention permits the weight given to the user-set task priority and to the priority based on recent task behavior to be varied as desired. The range value, the divider values, and the time-slice values are variable to permit tuning of the operating system.

Abstract: Protocols for communicating between a digital data processing system and a terminal. The terminal permits specification of attributes for characters, of fill characters and their attributes, of key board bit maps, and of different modes of specifying a group of shifted characters. The protocols include a protocol which takes another as an operand and specifies how the second protocol is to be executed, protocols which control the use of fill characters, a protocol which resets the attributes of a string of characters, protocols for shifting fields to the left and right and scrolling regions up and down, protocols which save and restore the current cursor state, protocols for loading bit maps and checking their correctness, a protocol for setting the current mode of specifying shifted characters, a protocol for setting the high bit of a following code, and a protocol for obtaining the attribute of the character at the current cursor position.

Abstract: What is disclosed is a memory module to and from which multibit binary words are stored and read out. Each multibit binary word comprises a standard byte size and one or more other memory bits that may be used for purposes such as parity checking. The modules may be mounted on a printed circuit mother board from which power, control signals and binary words are applied to and taken from the module.

Abstract: Emulation method and apparatus allowing a first system, which is not designed as a functional duplicate of a second system, to emulate the second system. The input/output structure of the second system is emulated in the first system by means of routines stored therein and which direct the already existing input/output structure to operate in the same manner as the input/output structure of the second system. The emulation routines are in turn invoked through the non-maskable interrupt mechanism of the first system by a modification thereto which detects the occurrence of "foreign" input/output requests; that is, input/output requests occuring in programs originally written for the second system and which are not normally recognized by the first system.

Abstract: Attachment apparatus for attaching a first object to a second object. The first object has a groove with parallel sides; the second object has attached thereto a spline with a flexible blade. When the spline is inserted in the groove, the blade exerts a force against one wall of the groove which forces the spline against the other wall, thereby retaining the spline in the groove. Also disclosed is label attachment apparatus employed generally to removably attach a label to a surface and specifically to removably attach a function key strip to a keyboard. The surface has a groove and the label has means which frictionally engage the groove. A preferred embodiment of the label attachment apparatus employs the groove, spline, and flexible blade as described above.

Abstract: An i/o handler providing communication between a host computer and a plurality of peripheral stations has a abutting member positioned adjacent to the computer and a distributing member removed from the computer. The two members are connected by a communication link with data paths and separate control paths. Communications on the link are by a protocol with synchronized time multiplexed channels and exchange of synchronizing signals in every frame. The handler minimizes the space required at the immediate site of the computer for external communications.

Abstract: A system bus and bus interface apparatus for connecting components in a data processing system having a plurality of non-memory and memory components. The system bus has the following sets of lines; A first plurality of lines carries a plurality of codes specifying a plurality of memory operations involving communications between a non-memory component and a memory component and a single code specifying an interprocessor communication between two non-memory components. A second plurality of lines carries an address in a memory component when the code on the first plurality of lines specifies a memory operation and a target address, an interprocessor communication type, and in some cases, a message, when the code on the first plurality of lines specifies an interprocessor communication.

Abstract: A memory system connected by means of a system bus to other components of a data processing system. The memory system includes a memory control unit and at least one memory unit in which information units containing two words are stored. The memory control unit is connected to the system bus and receives system addresses and memory commands from the system bus, and depending on the memory command, receives data from or provides data to the system bus. A memory bus and lines for control signals specifying memory requests connect the memory control unit and the memory unit. The memory bus is time multiplexed between memory addresses and information units. The memory control unit receives a memory command, a system address, and in the case of a write command, system data on the system bus and produces the memory requests, memory addresses, and information units required to carry out the memory command.

Abstract: A data structure for use in a document processing system corresponds to a document comprised of one or more Pages. Each Page is subdivided into one or more nonoverlapping Areas, each Area in turn being comprised of one or more types of Layers. Each Layer type is expressive of a particular type of information such as text or graphics information. Different Layer types may be superimposed to comprise the contents of an Area.

Abstract: A memory subsystem comprises pseudo-static memory chips operable in a low power self refresh mode or in a standby mode in which less access time is required. All memory chips are initially placed in the self refresh mode and are changed to the standby mode only when individually accessed. Then, the accessed chip is retained in the standby mode until such time as all chips are periodically returned to the self refresh mode. When a memory chip is first changed to the standby mode a delay time is provided to allow for the greater required access time. Thereafter, the memory chips which have then been placed in the standby mode are tracked by latching of addresses and comparison of the latched addresses to subsequently received addresses.