Patents Assigned to Wave Computing, Inc.
  • Patent number: 9960771
    Abstract: Disclosed embodiments select a proper hum frequency reference by utilizing one or more functional logic circuits within a cluster. The slowest logic circuit is determined, and an instance of that logic circuit is used in timing circuitry for the cluster. Multiple logic circuits with similar characteristics are incorporated into the timing circuit. Each cluster is interconnected to a second level timing circuit. Each cluster inputs timing information into the second level timing circuit. The second level timing circuit then determines when the next cycle, or tic, of the self-generated clock starts, and the process repeats, providing a self-generated clock signal.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: May 1, 2018
    Assignee: Wave Computing, Inc.
    Inventors: Gajendra Prasad Singh, Shaishav Desai
  • Patent number: 9933996
    Abstract: An apparatus for mathematical manipulation is described allowing the selective combination of shifters to shift binary numbers of various widths. Selective combination allows on-the-fly adjustment of shifters from independent to coordinated shifting operations. Selective combination allows adjustable hardware-based shifting while saving space and resources. Multiple eight-bit shifters can be configured for a variety of operand widths, such as a 32-bit width, a 24-bit width, a 16-bit width, or an eight-bit width. Multiplexers route the appropriate input data to the appropriate shifters. Opcodes configure the shifters for the desired type of shift and a shifted result is generated.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: April 3, 2018
    Assignee: Wave Computing, Inc.
    Inventor: Samit Chaudhuri
  • Patent number: 9692419
    Abstract: Compact logic evaluation gates are built using null convention logic (NCL) circuits. The inputs to a null convention circuit include a NCL true input and a NCL complement input. The NCL circuit includes a gate coupled to the pair of inputs, where the gate comprises a plurality of transistors. The transistors allow for logical signal capture, provide a pair of cross-coupled inverters for data storage, and include a first and second pull-down device. The first pull-down device causes a first side of the pair of cross-coupled inverters to go to a “0” state when a “1” is applied to the NCL true input, and the second pull-down device causes a second side of the pair of cross-coupled inverters to go to a “0” state when a “1” is applied to the NCL complement input.
    Type: Grant
    Filed: November 14, 2015
    Date of Patent: June 27, 2017
    Assignee: Wave Computing, Inc.
    Inventors: Benjamin Wiley Melton, Stephen Curtis Johnson
  • Patent number: 9588773
    Abstract: A processing device is provided. A cluster includes a plurality of groups of processing elements. A multi-word device is connected to the processing elements within the groups. Each processing element in a particular group is in communication with all other processing elements within the particular group, and only one of the processing elements within other groups in the cluster. Each processing element is limited to operations in which input bits can be processed and an output obtained without reference to other bits. The multi-word device is configured to cooperate with at least two other processing elements to perform processing that requires reference to other bits to obtain a result.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: March 7, 2017
    Assignee: Wave Computing, Inc.
    Inventors: Christopher John Nicol, Samit Chaudhuri, Radoslav Danilak
  • Patent number: 9590629
    Abstract: Clusters of logical elements are interconnected by a switching fabric. Each cluster contains processing elements, storage elements, and switching elements. A circular buffer within a cluster contains multiple switching instructions to control the flow of data throughout the switching fabric. The circular buffer provides a pipelined execution of switching instructions. Each cluster contains multiple processing elements, and each cluster further comprises an additional circular buffer for each processing element. Logical operations are controlled by the circular buffers.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: March 7, 2017
    Assignee: Wave Computing, Inc.
    Inventor: Christopher John Nicol
  • Patent number: 9563401
    Abstract: An extensible iterative multiplier design is provided. Embodiments provide cascaded 8-bit multipliers for simplifying the performance of multi-byte multiplications. Booth encoding is performed in the lowest order multiplier, with the result of the Booth encoding then provided to higher order multipliers. Additionally, multiply-add operations can be performed by initializing a partial product sum register. Configurable connections between the multipliers facilitate a variety of possible multiplication options, including the possibility of varying the width of the operands.
    Type: Grant
    Filed: December 7, 2013
    Date of Patent: February 7, 2017
    Assignee: Wave Computing, Inc.
    Inventors: Samit Chaudhuri, Radoslav Danilak
  • Patent number: 9385715
    Abstract: Multi-threshold flash Null Convention Logic (NCL) includes one or more high threshold voltage transistors within a flash NCL gate to reduce power consumption due to current leakage by transistors of the NCL gate. High-threshold voltage transistors may be added and/or may be used in place of one or more lower voltage threshold transistors of the NCL gate. A high-Vt device is included in the pull-up path to reduce power when the flash NCL logic gate is in the null state.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: July 5, 2016
    Assignee: Wave Computing, Inc.
    Inventor: Gajendra Prasad Singh