Abstract: A low noise amplifier circuit includes a first transistor, a second transistor, and a first inductor. The first transistor comprises a first terminal coupled to a first filtering circuit, a second terminal coupled to a second filtering circuit, and a control terminal configured to receive an input signal. The second transistor comprises a first terminal configured to output an output signal, a second terminal coupled to the first filtering circuit, and a control terminal. The first inductor includes a first terminal coupled to a high voltage terminal and a second terminal coupled to the first terminal of the second transistor. The second filtering circuit is coupled to a ground terminal.

Abstract: A high electron mobility transistor includes a III-V compound layer, a nitride layer, a source electrode, a drain electrode, a gate electrode, a surface plasma treatment region, and at least one moat. The nitride layer is disposed on the III-V compound layer. The source and the drain electrodes are disposed above the III-V compound layer. The gate electrode is disposed above the nitride layer. The moat is at least partially disposed in the nitride layer and between the source and the drain electrodes. The surface plasma treatment region is at least partially disposed in the nitride layer. The surface plasma treatment region is at least partially disposed at a top surface of the nitride layer between the moat and the drain electrode, a top surface of the nitride layer between the moat and the source electrode, and/or a top surface of the nitride layer under the moat.

Abstract: A high electron mobility transistor includes a first III-V compound layer, a second III-V compound layer, a source electrode, a drain electrode, a gate electrode, a first moat, and a second moat. The second III-V compound layer is disposed on the first III-V compound layer. The source electrode and the drain electrodes are disposed above the first III-V compound layer. The gate electrode is disposed above the second III-V compound layer located between the source and the drain electrodes in a first direction. The second III-V compound layer includes a first region under the gate electrode. The first moat is at least partially disposed between the first region and the source electrode in the first direction. The second moat is at least partially disposed between the first region and the drain electrode in the first direction.