Patents Assigned to Weebit Nano Ltd.
  • Patent number: 12224007
    Abstract: A method for determining a value of a manufacturing parameter of a resistive memory cell, the resistive memory cell including a stack of layers, includes providing reference memory cells corresponding to technological alternatives of the stack of layers; measuring for each reference memory cell an initial resistance value; determining for each reference memory cell a programming parameter value selected from among the resistance in a high resistance state and the programming window; establishing a relationship between the programming parameter and the initial resistance from the initial resistance values and the programming parameter values; and determining the manufacturing parameter value for which the programming parameter is greater than or equal to a target value, from the relationship between the programming parameter and the initial resistance and from a dependency relationship between the initial resistance and the manufacturing parameter.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: February 11, 2025
    Assignees: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES, WEEBIT NANO LTD
    Inventors: Gabriel Molas, Guiseppe Piccolboni, Amir Regev, Gaël Castellan, Jean-François Nodin
  • Patent number: 12170110
    Abstract: A memory including a memory array having a plurality of bit-line inputs and a plurality of word-line inputs; a bit-line decoder; and a control circuit is provided. The bit-line decoder includes a first circuit and a second circuit including a plurality of low-voltage field effect transistors (FET). The control circuit provides control signals to the plurality of low-voltage FETs in a sequence of a pre-pulse phase, a pulse phase, and a post-pulse phase, wherein at the pulse phase, the first circuit and the second circuit receives a desired voltage. The control circuit provide control signals the plurality of low-voltage FETs a voltage no greater than a low-voltage at the pre-pulse phase and the post-pulse phase. In silicon-on-insulator (SOI) technologies, use of low-voltage FETs in the bit-line and word-line decoders reduces the area of the periphery circuits of the memory array without requiring change to the memory array itself.
    Type: Grant
    Filed: November 18, 2022
    Date of Patent: December 17, 2024
    Assignee: Weebit Nano Ltd.
    Inventor: Lior Dagan
  • Patent number: 12165706
    Abstract: A method for resetting an array of RAM cells by applying a sequence of N reset operations, the method including at a first reset operation, defining a first reset technique and performing the first reset operation; at a j-th reset operation of a N?1 subsequent reset operations, j being an integer between 2 and N, if a correction yield of the reset technique used at the (j?1)-th reset operation fulfils a predefined condition, applying the reset technique used at the (j?1)-th reset operation to perform the j-th reset operation, if the correction yield does not fulfil the predefined condition, defining a new reset technique and applying the new reset technique to perform the j-th reset operation, the correction yield being a cumulative correction yield or a relative correction yield, the correction yield for the N reset operations being measured prior to the first reset operation.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: December 10, 2024
    Assignees: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES, WEEBIT NANO LTD
    Inventors: Gabriel Molas, Alessandro Bricalli, Guiseppe Piccolboni, Amir Regev
  • Patent number: 12131777
    Abstract: A resistive random-access memory (ReRAM) cell includes a field-effect transistor (FET) and a resistive element. The FET having a gate port, a drain port, and a source port. The gate port is connected to a word-line (WL) of the ReRAM cell, the source port is connected to a bit-line (BL) of the ReRAM cell, and a first port of the resistive element is connected to the drain of the FET. A second port of the resistive element is connected to a source-line (SL) of the ReRAM cell. During reset operation SL is connected to a high-voltage and BL to a low-voltage. During set operation SL is connected to a low-voltage and BL to a high-voltage. Using this common source configuration overcomes the requirement for a wider FET width of the prior art so as to accommodate the current supply needed during reset operation, and avoids overstressing of the FET.
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: October 29, 2024
    Assignee: Weebit Nano Ltd.
    Inventor: Lior Dagan
  • Patent number: 12119059
    Abstract: A method is provided for writing a data word to a resistive memory consisting of 2T2R differential cells each having first and second sets of a resistor (R) and a selection transistor (T). The method includes generating an initial codeword, programming it in 1T1R mode, checking its programming in 1T1R mode, inverting it, programming the inverted initial codeword in 1T1R mode, checking its programming in 1T1R mode, and reading, in 2T2R differential mode, that the read data correspond to said initial data. A device designed to implement this write method and to an electronic system including this device is also provided.
    Type: Grant
    Filed: November 20, 2022
    Date of Patent: October 15, 2024
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, WEEBIT NANO LTD
    Inventors: Bastien Giraud, Cyrille Laffond, Sebastien Ricavy, Valentin Gherman, Ilan Sever
  • Publication number: 20240331772
    Abstract: A programming circuitry for a resistor of a resistive random-access memory (ReRAM) is provided. The programming circuitry includes a current-limiting circuit; a current-terminating circuit including a current measurement circuit and a control circuit; and a voltage-limiting circuit, wherein the current-limiting circuit, the current-terminating circuit, and the voltage-limiting circuit operate in concert. Any one of the current-limiting circuit, the current-terminating circuit, and the voltage-limiting circuit may comprises an operational amplifier or a current conveyor.
    Type: Application
    Filed: June 12, 2024
    Publication date: October 3, 2024
    Applicant: Weebit Nano Ltd.
    Inventor: Lior DAGAN
  • Patent number: 12087360
    Abstract: A method for programming at least one resistive memory cell of an array of resistive memory cells, includes a sequence of N programming cycles, N being an integer greater than or equal to 2, each programming cycle including a set procedure and a reset procedure, each set procedure including the application of a set technique chosen among a plurality of set techniques, the method including acquiring a bit error ratio value corresponding to each programming cycle for each set technique; and at each programming cycle, applying the set technique having the lowest bit error ratio value corresponding to the programming cycle.
    Type: Grant
    Filed: June 3, 2022
    Date of Patent: September 10, 2024
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, WEEBIT NANO LTD
    Inventors: Gabriel Molas, Alessandro Bricalli, Guiseppe Piccolboni, Amir Regev
  • Patent number: 12068028
    Abstract: A resistive random-access memory (ReRAM) array with parallel reset and set programming and a method for programming is presented. The ReRAM array includes a plurality of ReRAM cells arranged in an array, wherein the array includes a plurality of rows and a plurality of columns, wherein at least two ReRAM cells of an array includes a word, wherein each ReRAM cell includes a select device having a control port, a first port, and a second port, and a resistive element; and a plurality of controllers, wherein the output of each of the plurality of controllers cause a reset programming or a set programming of the ReRAM cell in the column of the plurality of ReRAM cells that has the respective word line activated; such that the reset programming and the set programming occur in parallel.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: August 20, 2024
    Assignee: WEEBIT NANO LTD.
    Inventors: Lior Dagan, Ilan Sever
  • Patent number: 12052876
    Abstract: A memory includes a matrix of resistive memory cells and an interfacing device to interface the matrix, the interfacing device including at least a conversion capacitor, an electric source, a first switch and a second switch, the interfacing device being configured to: a) connect the conversion capacitor to the source by the second switch to charge the conversion capacitor, then, b) disconnect the conversion capacitor from the source and connect the conversion capacitor to the matrix to achieve a conversion between, on the one hand, a resistive state of one of the memory cells of the matrix, and, on the other hand, a state of charge of the conversion capacitor.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: July 30, 2024
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, WEEBIT NANO LTD
    Inventors: Anthonin Verdy, Gabriel Molas, Paola Trotti, Amir Regev
  • Patent number: 12040017
    Abstract: A programming circuitry for a resistor of a resistive random-access memory (ReRAM) is provided. The programming circuitry includes a current-limiting circuit; a current-terminating circuit including a current measurement circuit and a control circuit; and a voltage-limiting circuit, wherein the current-limiting circuit, the current-terminating circuit, and the voltage-limiting circuit operate in concert.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: July 16, 2024
    Assignee: Weebit Nano Ltd.
    Inventor: Lior Dagan
  • Patent number: 12033698
    Abstract: A method for resetting an array of Resistive Memory cells by applying a sequence of N reset operations, each reset operation including the application of a reset technique, the method including, at the first reset operation, performing the first reset operation by applying the reset technique having the highest relative correction yield; at the j-th reset operation of the N?1 subsequent reset operations, j being an integer number between 2 and N, defining a reset technique to be used at the j-th reset operation and performing the j-th reset operation.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: July 9, 2024
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, WEEBIT NANO LTD
    Inventors: Gabriel Molas, Alessandro Bricalli, Guiseppe Piccolboni, Amir Regev
  • Patent number: 11659720
    Abstract: A resistive random-access memory (ReRAM) array is provided. The ReRAM array includes a silicon over insulator (SOI) substrate; a first bit line; a first inverted bit line of the first bit line; a second bit line; a second inverted bit line of the second bit line; a first word line; a first inverted word line of the first word line; a first ReRAM cell comprising a first MOSFET, a second MOSFET, and a resistive element; and a second ReRAM cell comprising a first MOSFET, a second MOSFET, and a resistive element connected in series; wherein upon applying a predefined potential on elements of the first ReRAM cell, a state of the first ReRAM cell is adjusted without effecting a state of the second ReRAM.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: May 23, 2023
    Assignee: WEEBIT NANO LTD.
    Inventor: Lior Dagan
  • Publication number: 20230096127
    Abstract: A resistive random-access memory (ReRAM) cell includes a field-effect transistor (FET) and a resistive element. The FET having a gate port, a drain port, and a source port. The gate port is connected to a word-line (WL) of the ReRAM cell, the source port is connected to a bit-line (BL) of the ReRAM cell, and a first port of the resistive element is connected to the drain of the FET. A second port of the resistive element is connected to a source-line (SL) of the ReRAM cell. During reset operation SL is connected to a high-voltage and BL to a low-voltage. During set operation SL is connected to a low-voltage and BL to a high-voltage. Using this common source configuration overcomes the requirement for a wider FET width of the prior art so as to accommodate the current supply needed during reset operation, and avoids overstressing of the FET.
    Type: Application
    Filed: September 30, 2022
    Publication date: March 30, 2023
    Applicant: Weebit Nano Ltd.
    Inventor: Lior DAGAN
  • Patent number: 11538524
    Abstract: A resistive random-access memory (ReRAM) cell formed on a silicon over insulator substrate (SOI) is provided. The ReRAM includes a SOI substrate, a first MOSFET and a second MOSFET, each of which having a drain port, a gate port, a source port, and a bulk port. The drain port of the second MOSFET is connected to the source port of the first MOSFET; a first resistive element and a second resistive element, each having a first port and a second port, wherein the first ports of both resistive elements are connected to the drain of the first MOSFET; a first word line and a second word line connected to the gate port of the first MOSFET and the second MOSFET, respectively; and the state of the ReRAM cell is determined upon applying a predefined potential.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: December 27, 2022
    Assignee: Weebit Nano Ltd.
    Inventor: Lior Dagan
  • Publication number: 20220284955
    Abstract: A resistive random-access memory (ReRAM) array with parallel reset and set programming and a method for programming is presented. The ReRAM array includes a plurality of ReRAM cells arranged in an array, wherein the array includes a plurality of rows and a plurality of columns, wherein at least two ReRAM cells of an array includes a word, wherein each ReRAM cell includes a select device having a control port, a first port, and a second port, and a resistive element; and a plurality of controllers, wherein the output of each of the plurality of controllers cause a reset programming or a set programming of the ReRAM cell in the column of the plurality of ReRAM cells that has the respective word line activated; such that the reset programming and the set programming occur in parallel.
    Type: Application
    Filed: March 3, 2022
    Publication date: September 8, 2022
    Applicant: Weebit Nano Ltd.
    Inventors: Lior DAGAN, Ilan SEVER
  • Publication number: 20220238156
    Abstract: A programming circuitry for a resistor of a resistive random-access memory (ReRAM) is provided. The programming circuitry includes a current-limiting circuit; a current-terminating circuit including a current measurement circuit and a control circuit; and a voltage-limiting circuit, wherein the current-limiting circuit, the current-terminating circuit, and the voltage-limiting circuit operate in concert.
    Type: Application
    Filed: December 29, 2021
    Publication date: July 28, 2022
    Applicant: Weebit Nano Ltd.
    Inventor: Lior Dagan
  • Publication number: 20220122660
    Abstract: A semiconductor resistive random-access memory (ReRAM) device of an array including at least one ReRAM cell is provided. The ReRAM cell includes a word line; a select line; a first bit line; a second bit line having a polarity opposite of that of the first bit line; a first resistor having a first terminal and a second terminal, wherein the second terminal of the first resistor is connected to the first bit line; a second resistor having a first terminal and a second terminal, the second terminal of the second resistor is connected to the second bit line; and a transistor having a gate terminal, a source terminal and a drain terminal; the word line is connected to the gate terminal, the select line connected to the source terminal, and the drain terminal connected to the first terminal of the first resistor and the first terminal of the second resistor.
    Type: Application
    Filed: December 30, 2021
    Publication date: April 21, 2022
    Applicant: Weebit Nano Ltd.
    Inventor: Yoav NISSAN-COHEN
  • Publication number: 20220020815
    Abstract: A resistive random-access memory (ReRAM) array is provided. The ReRAM array includes a silicon over insulator (SOI) substrate; a first bit line; a first inverted bit line of the first bit line; a second bit line; a second inverted bit line of the second bit line; a first word line; a first inverted word line of the first word line; a first ReRAM cell comprising a first MOSFET, a second MOSFET, and a resistive element; and a second ReRAM cell comprising a first MOSFET, a second MOSFET, and a resistive element connected in series; wherein upon applying a predefined potential on elements of the first ReRAM cell, a state of the first ReRAM cell is adjusted without effecting a state of the second ReRAM.
    Type: Application
    Filed: July 12, 2021
    Publication date: January 20, 2022
    Applicant: Weebit Nano Ltd.
    Inventor: Lior DAGAN
  • Publication number: 20220020431
    Abstract: A resistive random-access memory (ReRAM) cell formed on a silicon over insulator substrate (SOI) is provided. The ReRAM includes a SOI substrate, a first MOSFET and a second MOSFET, each of which having a drain port, a gate port, a source port, and a bulk port. The drain port of the second MOSFET is connected to the source port of the first MOSFET; a first resistive element and a second resistive element, each having a first port and a second port, wherein the first ports of both resistive elements are connected to the drain of the first MOSFET; a first word line and a second word line connected to the gate port of the first MOSFET and the second MOSFET, respectively; and the state of the ReRAM cell is determined upon applying a predefined potential.
    Type: Application
    Filed: July 12, 2021
    Publication date: January 20, 2022
    Applicant: Weebit Nano Ltd.
    Inventor: Lior DAGAN