Abstract: During traditional programming of resistive random-access memory (ReRAM) arrays, many ReRAM cells are unnecessarily stressed. As a result of the overstress, the time dependent dielectric breakdown (TDDB) is low. According to an embodiment, negative voltages are used on the bit-line (BL) of the cell being programmed and on the and on all word-line (WL) of cells that are not being programmed. By doing so, it is possible to use a lower WL voltage and a lower source line (SL) voltage than is used in currently implemented solutions. As a result, stress on non-selected cells, and in particular transistors of non-selected cells, is reduced, thereby reducing TDDB.

Abstract: Stress and overprogramming of resistive random-access memory (ReRAM) cells is prevented by binned programming of each ReRAM cell (bit) of a ReRAM word. Accordingly, there is performed at least one read before write (RBW) of a low resistive state (LRS) of the ReRAM for each of the plurality of the word bits and at least one read before write (RBW) of a high resistive state (HRS) of the ReRAM for each of the plurality of the word bits. Then determination as to which bin of LRS bins and a plurality of HRS each bit belongs is based on the RBW results, and weakest and strongest bins are determined. Lastly, each bit of the word is programmed based on information provided, for example, from a lookup table (LUT) and the bin association of each bit. A ReRAM device may have a control logic that has embedded therein this method.

Abstract: A programming circuitry for a resistor of a resistive random-access memory (ReRAM) is provided. The programming circuitry includes a current-limiting circuit; a current-terminating circuit including a current measurement circuit and a control circuit; and a voltage-limiting circuit, wherein the current-limiting circuit, the current-terminating circuit, and the voltage-limiting circuit operate in concert. Any one of the current-limiting circuit, the current-terminating circuit, and the voltage-limiting circuit may comprises an operational amplifier or a current conveyor.

Abstract: The low-power fast wake-up band-gap reference voltage circuit operates in three phases: dormant, wake-up, and steady-state phases. The circuit enters wake-up subsequent to receipt of an enable signal which causes a one-shot timer to generate a slew enable signal pulse having a predetermined period. To a band-gap voltage reference circuitry comprising an operational amplifier, there is connected, at the wake-up phase, a boost circuitry, operative under the control of the slew enable signal that connects one or more of the one or more boost circuits to a band-gap voltage reference. Thereby, during the brief wake-up phase, more current is consumed to accelerate the response of the circuit. Upon completion of the wake-up phase the boost circuitry is disconnected under the control of the slew enable signal and for as long as the enable signal is active, the circuit is operative in a low-power mode.

Abstract: A memory including a memory array having a plurality of bit-line inputs and a plurality of word-line inputs; a bit-line decoder; and a control circuit is provided. The bit-line decoder includes a first circuit and a second circuit including a plurality of low-voltage field effect transistors (FET). The control circuit provides control signals to the plurality of low-voltage FETs in a sequence of a pre-pulse phase, a pulse phase, and a post-pulse phase, wherein at the pulse phase, the first circuit and the second circuit receives a desired voltage. The control circuit provide control signals the plurality of low-voltage FETs a voltage no greater than a low-voltage at the pre-pulse phase and the post-pulse phase. In silicon-on-insulator (SOI) technologies, use of low-voltage FETs in the bit-line and word-line decoders reduces the area of the periphery circuits of the memory array without requiring change to the memory array itself.

Abstract: A resistive random-access memory (ReRAM) cell includes a field-effect transistor (FET) and a resistive element. The FET having a gate port, a drain port, and a source port. The gate port is connected to a word-line (WL) of the ReRAM cell, the source port is connected to a bit-line (BL) of the ReRAM cell, and a first port of the resistive element is connected to the drain of the FET. A second port of the resistive element is connected to a source-line (SL) of the ReRAM cell. During reset operation SL is connected to a high-voltage and BL to a low-voltage. During set operation SL is connected to a low-voltage and BL to a high-voltage. Using this common source configuration overcomes the requirement for a wider FET width of the prior art so as to accommodate the current supply needed during reset operation, and avoids overstressing of the FET.

Abstract: A programming circuitry for a resistor of a resistive random-access memory (ReRAM) is provided. The programming circuitry includes a current-limiting circuit; a current-terminating circuit including a current measurement circuit and a control circuit; and a voltage-limiting circuit, wherein the current-limiting circuit, the current-terminating circuit, and the voltage-limiting circuit operate in concert. Any one of the current-limiting circuit, the current-terminating circuit, and the voltage-limiting circuit may comprises an operational amplifier or a current conveyor.

Abstract: A resistive random-access memory (ReRAM) array with parallel reset and set programming and a method for programming is presented. The ReRAM array includes a plurality of ReRAM cells arranged in an array, wherein the array includes a plurality of rows and a plurality of columns, wherein at least two ReRAM cells of an array includes a word, wherein each ReRAM cell includes a select device having a control port, a first port, and a second port, and a resistive element; and a plurality of controllers, wherein the output of each of the plurality of controllers cause a reset programming or a set programming of the ReRAM cell in the column of the plurality of ReRAM cells that has the respective word line activated; such that the reset programming and the set programming occur in parallel.

Abstract: A programming circuitry for a resistor of a resistive random-access memory (ReRAM) is provided. The programming circuitry includes a current-limiting circuit; a current-terminating circuit including a current measurement circuit and a control circuit; and a voltage-limiting circuit, wherein the current-limiting circuit, the current-terminating circuit, and the voltage-limiting circuit operate in concert.

Abstract: A resistive random-access memory (ReRAM) array is provided. The ReRAM array includes a silicon over insulator (SOI) substrate; a first bit line; a first inverted bit line of the first bit line; a second bit line; a second inverted bit line of the second bit line; a first word line; a first inverted word line of the first word line; a first ReRAM cell comprising a first MOSFET, a second MOSFET, and a resistive element; and a second ReRAM cell comprising a first MOSFET, a second MOSFET, and a resistive element connected in series; wherein upon applying a predefined potential on elements of the first ReRAM cell, a state of the first ReRAM cell is adjusted without effecting a state of the second ReRAM.

Abstract: A resistive random-access memory (ReRAM) cell includes a field-effect transistor (FET) and a resistive element. The FET having a gate port, a drain port, and a source port. The gate port is connected to a word-line (WL) of the ReRAM cell, the source port is connected to a bit-line (BL) of the ReRAM cell, and a first port of the resistive element is connected to the drain of the FET. A second port of the resistive element is connected to a source-line (SL) of the ReRAM cell. During reset operation SL is connected to a high-voltage and BL to a low-voltage. During set operation SL is connected to a low-voltage and BL to a high-voltage. Using this common source configuration overcomes the requirement for a wider FET width of the prior art so as to accommodate the current supply needed during reset operation, and avoids overstressing of the FET.

Abstract: A resistive random-access memory (ReRAM) cell formed on a silicon over insulator substrate (SOI) is provided. The ReRAM includes a SOI substrate, a first MOSFET and a second MOSFET, each of which having a drain port, a gate port, a source port, and a bulk port. The drain port of the second MOSFET is connected to the source port of the first MOSFET; a first resistive element and a second resistive element, each having a first port and a second port, wherein the first ports of both resistive elements are connected to the drain of the first MOSFET; a first word line and a second word line connected to the gate port of the first MOSFET and the second MOSFET, respectively; and the state of the ReRAM cell is determined upon applying a predefined potential.

Abstract: A resistive random-access memory (ReRAM) array with parallel reset and set programming and a method for programming is presented. The ReRAM array includes a plurality of ReRAM cells arranged in an array, wherein the array includes a plurality of rows and a plurality of columns, wherein at least two ReRAM cells of an array includes a word, wherein each ReRAM cell includes a select device having a control port, a first port, and a second port, and a resistive element; and a plurality of controllers, wherein the output of each of the plurality of controllers cause a reset programming or a set programming of the ReRAM cell in the column of the plurality of ReRAM cells that has the respective word line activated; such that the reset programming and the set programming occur in parallel.

Abstract: A programming circuitry for a resistor of a resistive random-access memory (ReRAM) is provided. The programming circuitry includes a current-limiting circuit; a current-terminating circuit including a current measurement circuit and a control circuit; and a voltage-limiting circuit, wherein the current-limiting circuit, the current-terminating circuit, and the voltage-limiting circuit operate in concert.

Abstract: A semiconductor resistive random-access memory (ReRAM) device of an array including at least one ReRAM cell is provided. The ReRAM cell includes a word line; a select line; a first bit line; a second bit line having a polarity opposite of that of the first bit line; a first resistor having a first terminal and a second terminal, wherein the second terminal of the first resistor is connected to the first bit line; a second resistor having a first terminal and a second terminal, the second terminal of the second resistor is connected to the second bit line; and a transistor having a gate terminal, a source terminal and a drain terminal; the word line is connected to the gate terminal, the select line connected to the source terminal, and the drain terminal connected to the first terminal of the first resistor and the first terminal of the second resistor.

Abstract: A resistive random-access memory (ReRAM) array is provided. The ReRAM array includes a silicon over insulator (SOI) substrate; a first bit line; a first inverted bit line of the first bit line; a second bit line; a second inverted bit line of the second bit line; a first word line; a first inverted word line of the first word line; a first ReRAM cell comprising a first MOSFET, a second MOSFET, and a resistive element; and a second ReRAM cell comprising a first MOSFET, a second MOSFET, and a resistive element connected in series; wherein upon applying a predefined potential on elements of the first ReRAM cell, a state of the first ReRAM cell is adjusted without effecting a state of the second ReRAM.

Abstract: A resistive random-access memory (ReRAM) cell formed on a silicon over insulator substrate (SOI) is provided. The ReRAM includes a SOI substrate, a first MOSFET and a second MOSFET, each of which having a drain port, a gate port, a source port, and a bulk port. The drain port of the second MOSFET is connected to the source port of the first MOSFET; a first resistive element and a second resistive element, each having a first port and a second port, wherein the first ports of both resistive elements are connected to the drain of the first MOSFET; a first word line and a second word line connected to the gate port of the first MOSFET and the second MOSFET, respectively; and the state of the ReRAM cell is determined upon applying a predefined potential.