Patents Assigned to Weifang Goertek Microelectronics Co., Ltd.
  • Patent number: 12107053
    Abstract: Disclosed is a shielding process for SIP packaging, including: providing a circuit board; cutting the covering layer to form half-cut trenches separating different SIP packaging modules from each other, and to form grooves in each single SIP packaging module; forming a metal overlay, the metal overlay on an outer surface of the SIP packaging module and at positions where the half-cut trenches are located constituting a conformal shielding, the metal overlay at positions where the grooves are located constituting a compartment shielding; and cutting the half-cut trenches to obtain a plurality of SIP packaging modules that are separate from each other.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: October 1, 2024
    Assignee: Weifang Goertek Microelectronics Co., Ltd.
    Inventors: Juncheng Guo, Dewen Tian, Qinglin Song
  • Patent number: 12074037
    Abstract: Disclosed is a packaging method for circuit units, wherein the circuit units comprise a silicon layer substrate and a silicon dioxide layer overlaid on the silicon layer substrate. The packaging method for a circuit unit comprises: attaching a plurality of circuit units to a circuit baseplate in a spaced and inverted mode, wherein the silicon dioxide layer is attached to the circuit baseplate, and the silicon layer substrate faces away from the circuit baseplate; forming an insulator between the circuit units; removing the silicon layer substrate to expose the silicon dioxide layer; and forming an electromagnetic shielding layer on the silicon dioxide layer and the insulator.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: August 27, 2024
    Assignee: Weifang Goertek Microelectronics Co., Ltd.
    Inventors: Haisheng Wang, Dewen Tian, Qinglin Song
  • Patent number: 12031920
    Abstract: Disclosed is a method for detecting coverage rate of an intermetallic compound, the method comprising putting a chip subjected to wire bonding into a mixed reagent of fuming nitric acid and fuming sulfuric acid for soaking, wherein the chip subjected to wire bonding comprises a silver wire and an aluminum; taking out the chip after the silver wire is removed; and detecting the coverage rate of an intermetallic compound on the aluminum pad.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: July 9, 2024
    Assignee: Weifang Goertek Microelectronics Co., Ltd.
    Inventors: Dingguo Zhong, Dewen Tian, Qinglin Song
  • Patent number: 12002685
    Abstract: Disclosed is a method for packaging a chip, comprising the following steps: providing a baseplate formed with an open slot thereon penetrating through opposite sides of the baseplate; providing a release base material, wherein the release base material is bonded to a first side of the baseplate and covers the open slot; providing a chip, wherein the chip is mounted on the release base material at the position of the open slot; packaging a second side of the baseplate facing away from the release base material so as to form a packaging layer which packages the chip and fixes it on the baseplate; removing the release base material so as to obtain a package structure for the chip.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: June 4, 2024
    Assignee: Weifang Goertek Microelectronics Co., Ltd.
    Inventors: Baoguan Yin, Fei She, Dewen Tian, Qinglin Song
  • Patent number: 11985486
    Abstract: Disclosed are a microphone array-based sound signal processing method, apparatus and device. The method comprises: selecting, from a microphone array, a target microphone combination which is used for receiving a sound signal of a target sound source, the target microphone combination comprising a first microphone and at least one second microphone; obtaining target compensation information corresponding to the target microphone combination, the target compensation information comprising a signal compensation parameter of each second microphone with respect to the first microphone; according to the target compensation information, performing signal compensation processing on a second sound signal received by means of the second microphone; and according to the second sound signal subjected to the signal compensation processing and a first sound signal received by means of the first microphone, obtaining a target sound signal and outputting same.
    Type: Grant
    Filed: September 29, 2019
    Date of Patent: May 14, 2024
    Assignee: Weifang Goertek Microelectronics Co., Ltd.
    Inventor: Xiaohong Zhang
  • Patent number: 11882397
    Abstract: Disclosed are a noise reduction method for a microphone array of an earphone, an apparatus, and an earphone comprising: acquiring, when an earphone wearer speaks, a first sound signal collected by a bone conduction microphone arranged on the earphone and second sound signals collected respectively by a preset number of microphones arranged on the earphone; determining, according to the first sound signal and the second sound signal, a delay time from a time when the voice signal arrives at each microphone to a time when the voice signal arrives at the bone conduction microphone; computing, according to the delay time, a pointing angle of the microphone array formed by the microphones relative to the wearer's mouth; and adjusting a beam pointing angle of the microphone array according to the pointing angle, such that the microphone array forms a beam by an adjusted beam pointing angle.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: January 23, 2024
    Assignee: Weifang Goertek Microelectronics Co. Ltd.
    Inventor: Guangpeng Tie
  • Patent number: 11882681
    Abstract: Disclosed are an electromagnetic shielding structure and a manufacturing method thereof, and an electronic product. The manufacturing method includes covering an injection mold on a circuit substrate, so that different circuit units on the circuit substrate are respectively accommodated in different injection molding cavities of the injection mold; injecting a non-conductive plastic sealant into the injection molding cavities so as to form non-conductive plastic sealing bodies on the circuit units, wherein spacing grooves are formed between the non-conductive plastic sealing bodies; and forming a conductive shielding layer on the non-conductive plastic sealing bodies, so that the conductive shielding layer covers the non-conductive plastic sealing bodies and fills the spacing grooves to form shielding barrier walls, thereby realizing shielding between the different circuit units in respective cavities.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: January 23, 2024
    Assignee: Weifang Goertek Microelectronics Co. Ltd.
    Inventors: Kaiwei Wang, Dewen Tian, Qinglin Song
  • Patent number: 11757456
    Abstract: Disclosed is a phase-locked loop circuit, including: a phase-locked loop, a locking detection circuit, an input end for inputting a reference clock signal, a first output end for outputting an oscillator clock signal, and a second output end for outputting a locking signal, wherein the phase-locked loop is configured to output the oscillator clock signal according to the reference clock signal and control the reference clock signal and the oscillator clock signal to be synchronous; and the locking detection circuit is configured to output the locking signal to the second output end when the oscillator clock signal and the reference clock signal are synchronous.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: September 12, 2023
    Assignee: Weifang Goertek Microelectronics Co., Ltd.
    Inventors: Mingyong Shi, Zhiyou Xu, Lide Wu
  • Patent number: 11722808
    Abstract: Disclosed is a micro-filter comprising a substrate with a back cavity and a film layer provided on the substrate and suspended above the back cavity; the film layer has through holes distributed thereon, and is made of an amorphous metal film. Also disclosed is an acoustic device comprising the micro-filter.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: August 8, 2023
    Assignee: Weifang Goertek Microelectronics Co., Ltd.
    Inventor: Yujing Lin
  • Publication number: 20230041430
    Abstract: Disclosed is a MEMS chip that in certain embodiments includes a substrate with a back cavity, and a plate capacitor bank provided on the substrate; the plate capacitor bank at least includes a first plate capacitor structure and a second plate capacitor structure located below the first plate capacitor structure and arranged in parallel with the first plate capacitor structure; the first plate capacitor structure includes a first diaphragm and a first hack electrode; and the second plate capacitor structure includes a second. diaphragm and a second back electrode.
    Type: Application
    Filed: April 1, 2020
    Publication date: February 9, 2023
    Applicant: Weifang Goertek Microelectronics Co., Ltd.
    Inventors: GUANXUN QIU, Ansheng Wu, Bo Liu
  • Publication number: 20220406619
    Abstract: Disclosed is a packaging method for circuit units, wherein the circuit units comprise a silicon layer substrate and a silicon dioxide layer overlaid on the silicon layer substrate. The packaging method for a circuit unit comprises: attaching a plurality of circuit units to a circuit baseplate in a spaced and inverted mode, wherein the silicon dioxide layer is attached to the circuit baseplate, and the silicon layer substrate faces away from the circuit baseplate; forming an insulator between the circuit units; removing the silicon layer substrate to expose the silicon dioxide layer; and forming an electromagnetic shielding layer on the silicon dioxide layer and the insulator.
    Type: Application
    Filed: December 6, 2019
    Publication date: December 22, 2022
    Applicant: Weifang Goertek Microelectronics Co., Ltd.
    Inventors: Haisheng Wang, Dewen Tian, Qinglin Song
  • Publication number: 20220408549
    Abstract: Disclosed is a packaging structure for circuit units, comprising: a circuit baseplate, wherein the circuit baseplate is provided thereon with a circuit unit, the circuit unit including a silicon dioxide layer and an electronic device arranged on the silicon dioxide layer; an insulator, wherein the insulator surrounds the circuit unit; and an electromagnetic shielding layer, wherein the electromagnetic shielding layer covers the circuit unit and the insulator.
    Type: Application
    Filed: December 6, 2019
    Publication date: December 22, 2022
    Applicant: Weifang Goertek Microelectronics Co., Ltd.
    Inventors: Haisheng Wang, Dewen Tian, Qinglin Song
  • Publication number: 20220388836
    Abstract: Disclosed are a MEMS chip and an electronic device. The chip can include a substrate having a back cavity, as well as a back electrode and an induction membrane both disposed on the substrate, wherein the back electrode and the induction membrane are located on the back cavity and constitute a capacitor structure, the induction membrane comprises an active area opposite to the back cavity, an inactive area disposed outside the active area, and an isolation area located between the active area and the inactive area, and the isolation area comprises two insulation loops connected to the active area and the inactive area respectively, and a buffer area connected between the two insulation loops, both of the insulation loops being disposed around the active area.
    Type: Application
    Filed: October 9, 2019
    Publication date: December 8, 2022
    Applicant: Weifang Goertek Microelectronics Co., Ltd.
    Inventors: BO Liu, Ansheng Wu
  • Publication number: 20220377442
    Abstract: Disclosed is a micro-filter comprising a substrate with a back cavity and a film layer provided on the substrate and suspended above the back cavity; the film layer has through holes distributed thereon, and is made of an amorphous metal film. Also disclosed is an acoustic device comprising the micro-filter.
    Type: Application
    Filed: July 5, 2019
    Publication date: November 24, 2022
    Applicant: Weifang Goertek Microelectronics Co., Ltd.
    Inventor: YUJING LIN
  • Publication number: 20220367209
    Abstract: Disclosed is a method for packaging a chip, comprising the following steps: providing a baseplate formed with an open slot thereon penetrating through opposite sides of the baseplate; providing a release base material, wherein the release base material is bonded to a first side of the baseplate and covers the open slot; providing a chip, wherein the chip is mounted on the release base material at the position of the open slot; packaging a second side of the baseplate facing away from the release base material so as to form a packaging layer which packages the chip and fixes it on the baseplate; removing the release base material so as to obtain a package structure for the chip.
    Type: Application
    Filed: December 6, 2019
    Publication date: November 17, 2022
    Applicant: Weifang Goertek Microelectronics Co., Ltd.
    Inventors: Baoguan Yin, Fei She, Dewen Tian, Qinglin Song
  • Publication number: 20220360883
    Abstract: Disclosed are a noise reduction method for a microphone array of an earphone, an apparatus, and an earphone comprising: acquiring, when an earphone wearer speaks, a first sound signal collected by a bone conduction microphone arranged on the earphone and second sound signals collected respectively by a preset number of microphones arranged on the earphone; determining, according to the first sound signal and the second sound signal, a delay time from a time when the voice signal arrives at each microphone to a time when the voice signal arrives at the bone conduction microphone; computing, according to the delay time, a pointing angle of the microphone array formed by the microphones relative to the wearer's mouth; and adjusting a beam pointing angle of the microphone array according to the pointing angle, such that the microphone array forms a beam by an adjusted beam pointing angle.
    Type: Application
    Filed: September 26, 2019
    Publication date: November 10, 2022
    Applicant: Weifang Goertek Microelectronics Co., Ltd.
    Inventor: Guangpeng TIE
  • Publication number: 20220254731
    Abstract: Disclosed is a shielding process for SIP packaging, including: providing a circuit board; cutting the covering layer to form half-cut trenches separating different SIP packaging modules from each other, and to form grooves in each single SIP packaging module; forming a metal overlay, the metal overlay on an outer surface of the SIP packaging module and at positions where the half-cut trenches are located constituting a conformal shielding, the metal overlay at positions where the grooves are located constituting a compartment shielding; and cutting the half-cut trenches to obtain a plurality of SIP packaging modules that are separate from each other.
    Type: Application
    Filed: December 6, 2019
    Publication date: August 11, 2022
    Applicant: Weifang Goertek Microelectronics Co., Ltd.
    Inventors: Juncheng Guo, Dewen Tian, Qinglin Song
  • Publication number: 20220246015
    Abstract: Disclosed are fall detection method and apparatus (400), and a wearable device (100). The method comprising: acquiring air pressure data of a position where a wearable device (100) is located, and performing first fall detection according to the air pressure data to obtain a first detection result (S2100); acquiring an attitude angle of the wearable device in the case that the first detection result is that fall has occurred, and performing second fall detection according to the attitude angle to obtain a second detection result (S2200); and determining a fall detection result according to the first detection result and the second detection result (S2300).
    Type: Application
    Filed: December 6, 2019
    Publication date: August 4, 2022
    Applicant: Weifang Goertek Microelectronics Co. Ltd.
    Inventors: Dexin Wang, Susu Di, Xuejun Zhang
  • Publication number: 20220248573
    Abstract: Disclosed are an electromagnetic shielding structure and a manufacturing method thereof, and an electronic product. The manufacturing method comprising the following steps: covering an injection mold on a circuit substrate, so that different circuit units on the circuit substrate are respectively accommodated in different injection molding cavities of the injection mold; injecting a non-conductive plastic sealant into the injection molding cavities so as to form non-conductive plastic sealing bodies on the circuit units, wherein spacing grooves are formed between the non-conductive plastic sealing bodies; and forming a conductive shielding layer on the non-conductive plastic sealing bodies, so that the conductive shielding layer covers the non-conductive plastic sealing bodies and fills the spacing grooves to form shielding barrier walls, thereby realizing shielding between the different circuit units in respective cavities.
    Type: Application
    Filed: December 6, 2019
    Publication date: August 4, 2022
    Applicant: Weifang Goertek Microelectronics Co., Ltd.
    Inventors: Kaiwei Wang, Dewen Tian, Qinglin Song
  • Publication number: 20220231693
    Abstract: Disclosed is a phase-locked loop circuit, including: a phase-locked loop, a locking detection circuit, an input end for inputting a reference clock signal, a first output end for outputting an oscillator clock signal, and a second output end for outputting a locking signal, wherein the phase-locked loop is configured to output the oscillator clock signal according to the reference clock signal and control the reference clock signal and the oscillator clock signal to be synchronous; and the locking detection circuit is configured to output the locking signal to the second output end when the oscillator clock signal and the reference clock signal are synchronous.
    Type: Application
    Filed: December 30, 2019
    Publication date: July 21, 2022
    Applicant: Weifang Goertek Microelectronics Co. Ltd.
    Inventors: MINGYONG Shi, Zhiyou Xu, Lide Wu