Abstract: A multi-CPU system capable of facilitating a change of a program for each of CPUs of a slave-side section and constructing a control program on a side of only a slave-side section, to thereby facilitate preparation of the control program. A shared memory is connected to buses, resulting in a multi-CPU system being separated into a master-side section and a slave-side section, with the shared memory being interposed therebetween. A measure/control function blocks connected to a measured/controlled equipment and a ROM stored therein with an activation program for down-loading a program to a RAM of a slave CPU block are connected to the bus for the slave-side section. Then, the RAM is stored therein with the program down-loaded through the buses, resulting in the measured/controlled equipment being controlled according to the program.

Abstract: A multi-CPU device capable of automatically carrying out normal shutdown of a general purpose OS when feed of a current from a main power supply is interrupted while being significantly reduced in manufacturing cost. The multi-CPU device includes a master CPU block mounted therein with a general purpose OS, a slave CPU block mounted therein with a realtime OS, and a unit for controlling a controlled equipment based on the realtime OS. The multi-CPU device also includes a UPS provided with a realtime OS interface. The realtime OS outputs a DC current from a battery to the master CPU block and slave CPU block when the service interruption sensing circuit of the UPS senses service interruption. The realtime OS interface outputs a service interruption sensing signal to the realtime OS, so that the realtime OS which detected service interruption shuts down the general purpose OS.