Abstract: Methods of fabricating a plurality of carbon nanotube-bundle probes on a substrate are disclosed. In some embodiments, the method includes the following: providing a substrate having a top surface and a bottom surface; forming an array of electrically conductive pads on the top surface, the array of electrically conductive pads being formed to mirror an array of pads on an integrated circuit that is to be tested; applying a catalyst for promoting growth of carbon nanotubes on each of the array of electrically conductive pads; heating the substrate in a carbon-rich environment thereby growing nanotubes extending upwardly from each of the array of electrically conductive pads and above the top surface of the substrate thereby forming a plurality of carbon nanotube-bundle probes extending upwardly above the top surface of the substrate; and capping each of the plurality of carbon nanotube-bundle probes with an electrically conductive material.

Abstract: Methods of fabricating a plurality of carbon nanotube-bundle probes on a substrate are disclosed. In some embodiments, the method includes the following: providing a substrate having a top surface and a bottom surface; forming an array of electrically conductive pads on the top surface, the array of electrically conductive pads being formed to mirror an array of pads on an integrated circuit that is to be tested; applying a catalyst for promoting growth of carbon nanotubes on each of the array of electrically conductive pads; heating the substrate in a carbon-rich environment thereby growing nanotubes extending upwardly from each of the array of electrically conductive pads and above the top surface of the substrate thereby forming a plurality of carbon nanotube-bundle probes extending upwardly above the top surface of the substrate; and capping each of the plurality of carbon nanotube-bundle probes with an electrically conductive material.

Abstract: Methods of fabricating a plurality of carbon nanotube-bundle probes on a substrate are disclosed. In some embodiments, the method includes the following: providing a substrate having a top surface and a bottom surface; forming an array of electrically conductive pads on the top surface, the array of electrically conductive pads being formed to mirror an array of pads on an integrated circuit that is to be tested; applying a catalyst for promoting growth of carbon nanotubes on each of the array of electrically conductive pads; heating the substrate in a carbon-rich environment thereby growing nanotubes extending upwardly from each of the array of electrically conductive pads and above the top surface of the substrate thereby forming a plurality of carbon nanotube-bundle probes extending upwardly above the top surface of the substrate; and capping each of the plurality of carbon nanotube-bundle probes with an electrically conductive material.

Abstract: A probe card assembly for testing circuit boards is disclosed. In some embodiments, the assembly includes the following: a multi-layered dielectric plate aligned with an integrated circuit, the integrated circuit having on its surface a first plurality of electrical contacts arranged in a pattern, the dielectric plate having arrayed upon its surface a second plurality of electrical contacts arranged in a pattern substantially matching the first plurality of electrical contacts; a nanotube interposer interposed between the dielectric plate and the integrated circuit, the nanotube interposer having compliant carbon nanotubes that are arranged to match the pattern of electrical contacts on the integrated circuit and the dielectric plate; and a plurality of vertical probes arrayed upon the nanotube interposer and joined with the nanotubes, the vertical probes making electrical contact with the first plurality of electrical contacts and the second plurality of electrical contacts via the nanotubes.

Abstract: Methods and systems for inserting and replacing swaged probe pins in a lower die portion of a head having an array of micro-holes for receiving the probe pins are disclosed. The methods and systems include the following: swaged probe pins including substantially cylindrical ends and a swaged center portion; and an assembly aid film including an array of slotted holes, each of the slotted holes including a substantially round portion for receiving the substantially cylindrical ends of the swaged probe pins and slot portions for receiving the swaged center portion of the swaged probe pins. The array of slotted holes is configured to properly align the swaged probe pins with the array of micro-holes.

Abstract: An upper die portion of a die head for aligning probes having different offsets in a first array of first micro-holes formed in a lower die portion of the die head. The upper die portion includes a spacer portion and a first assembly aid film. The spacer portion includes first and second surfaces. The first surface contacts the lower die portion. The first assembly aid film is attached with the second surface and has a second array of second micro-holes for receiving the probes having different offsets. The second micro-holes include at least a first micro-hole that is configured to be offset from a corresponding micro-hole of the first micro-holes by a first offset and at least a second micro-hole that is configured to be offset from a corresponding micro-hole of the first micro-holes by a second offset that is not the same as the first offset.

Abstract: An upper die portion of a die head for aligning probes having different offsets in a first array of first micro-holes formed in a lower die portion of the die head. The upper die portion includes a spacer portion and a first assembly aid film. The spacer portion includes first and second surfaces. The first surface contacts the lower die portion. The first assembly aid film is attached with the second surface and has a second array of second micro-holes for receiving the probes having different offsets. The second micro-holes include at least a first micro-hole that is configured to be offset from a corresponding micro-hole of the first micro-holes by a first offset and at least a second micro-hole that is configured to be offset from a corresponding micro-hole of the first micro-holes by a second offset that is not the same as the first offset.

Abstract: An improved device for cleaning probe pins of a probe head assembly is presented. The device includes a first holding plate, a second holding plate and a cleaning cartridge. The first holding plate secures the probe head assembly. The second holding plate secures the cleaning cartridge in proximity to the first holding plate. The cleaning cartridge has a chamber. The chamber includes a cleaning solution and an absorbent pad located therein. The absorbent pad is saturated with the cleaning solution and prevents leakage of the cleaning solution out of the chamber. During cleaning operations, the first holding plate is positioned about the second holding plate such that the probe pins of a probe head extend into and contact the absorbent pad in the chamber. Once contact is established, the cleaning solution acts upon the probe pin tips to remove unwanted debris. A depth of penetration of the pins into the pad is controlled by a surface of the cartridge.

Abstract: An upper die portion of a die head for aligning probe pins in first array of first micro-holes formed in lower die portion of the die head, which generally includes a spacer portion and is adapted to contact lower die portion is typically positioned between second surface and support frame and includes a second array of second micro-holes adapted to receive probe pins generally is in contact or close proximity to first assembly aid film and has a third array of third micro-holes adapted to receive probe pins and third array of third micro-holes are patterned to align with one another but are both offset with first array of first micro-holes by approximately the lateral distance between probe tip and probe head.

Abstract: A space transformer for electrically interconnecting a probe head to a printed circuit board, which includes a flexible multilayer circuit with device under test contact pads formed on a first side and printed circuit board contact pads formed on a second side. Electrically conductive circuit traces extend between the device under test contact pads and the printed circuit board contact pads. A shim plate is fastened to a periphery of the first side of the flexible multilayer circuit and a bottom plate is fastened to a periphery of the second side of the flexible multilayer circuit. The bottom plate has a plurality of internal apertures are aligned with the printed circuit board contact pads separated by bottom plate stanchions that are aligned with the device under test contact pads. A plurality of interconnects are bonded and electrically interconnected to the printed circuit contact pads and extend through the internal apertures.

Abstract: An upper die portion (36) of a die head for aligning probe pins (14) in first array of first micro-holes (18) formed in lower die portion (12) of the die head, which generally includes a spacer portion (38), a support frame (40), and first and second assembly aid films (42) and (44), respectively. Spacer portion (38) is adapted to contact lower die portion (12). First assembly aid film (42) is typically positioned between second surface (48) and support frame (40) and includes a second array of second micro-holes (50) adapted to receive probe pins (14). Second assembly aid film (44) generally is in contact or close proximity to first assembly aid film (42) and has a third array of third micro-holes (52) adapted to receive probe pins (14). Second array of second micro-holes (50) and third array of third micro-holes (52) are patterned to align with one another but are both offset with first array of first micro-holes (18) by approximately the lateral distance between probe tip (20) and probe head (28).

Abstract: A probe head for testing the properties of a semiconducting device (10) under test including a dielectric film (24) supporting at least one semiconducting device (10) under test with a support frame (26) tautly supporting the dielectric film (24). A first support (40) positions a first probe (28) for electrically contacting a first side (16) of the semiconducting device (10) under test and a second support (34), having a actuator to move a second probe (30) between a first position (P1) and a second position (P2), positions second probe (30) with the second position (P2) being for electrically contacting an opposing second side (18) of the semiconductor device under test.

Abstract: A method of manufacturing a probe test head for testing of semiconductor integrated circuits includes: defining shapes of a plurality of probes as one or more masks; a step for fabricating the plurality of probes using the mask; and disposing the plurality of probes through corresponding holes in a first die and a second die. The step for fabricating the plurality of probes may include one of photo-etching and photo-defined electroforming.

Abstract: An improved vertical pin probing device is constructed with a housing with spaced upper and lower spacers of a metal alloy, each having a thin sheet of silicon nitride ceramic material held in a window in the spacer of adhesive. The spacers may be composed of foils adhered to one another in a laminated structure. The sheets of silicon nitride have laser-drilled matching patterns of holes supporting probe pins and insulating the probe pins from the housing. The spacers and silicon nitride ceramic sheets have coefficients of thermal expansion closely matching that of the silicon chip being probed, so that the probing device compensates for temperature variations over a large range of probing temperatures.

Abstract: A method of fabricating a plurality of micro probes comprising the steps of defining the shapes of a plurality of probes as a mask, applying a photoresist to a surface of a metal foil, overlaying the mask on the metal foil, exposing the photoresist to light passed through the mask, developing the photoresist, removing a portion of the photoresist to expose a portion of the metal foil, applying an etcher to the surface of the metal foil to remove the exposed portion to produce a plurality of probes, and chemically polishing and plating the plurality of probes.

Abstract: A method of manufacturing a probe test head for testing of semiconductor integrated circuits includes: defining shapes of a plurality of probes as one or more masks; a step for fabricating the plurality of probes using the mask; and disposing the plurality of probes through corresponding holes in a first die and a second die. The step for fabricating the plurality of probes may include one of photo-etching and photo-defined electroforming.

Abstract: An improved device for cleaning probe pins of a probe head assembly is presented. The device includes a first holding plate, a second holding plate and a cleaning cartridge. The first holding plate secures the probe head assembly. The second holding plate secures the cleaning cartridge in proximity to the first holding plate. The cleaning cartridge has a chamber. The chamber includes a cleaning solution and an absorbent pad located therein. The absorbent pad is saturated with the cleaning solution and prevents leakage of the cleaning solution out of the chamber. During cleaning operations, the first holding plate is positioned about the second holding plate such that the probe pins of a probe head extend into and contact the absorbent pad in the chamber. Once contact is established, the cleaning solution acts upon the probe pin tips to remove unwanted debris. A depth of penetration of the pins into the pad is controlled by a surface of the cartridge.

Abstract: A probe card assembly that compensates for differing rates of thermal expansion is disclosed herein. The assembly is comprised of a multi-layered dielectric plate interposed between a probe head and a printed circuit board. The printed circuit board has arrayed upon its surface a first plurality of electrical contacts arranged in a pattern. The dielectric plate has a second plurality of electrical contacts arranged in a pattern matching the first plurality of contacts. A planarizing interposer is interposed between the plate and the printed circuit board and has a pattern of holes matching the pattern of electrical contacts on the printed circuit board and plate. The assembly further includes a plurality of electrical connectors disposed within each of the holes arrayed in a pattern upon the planarizing interposer a plurality conductive bumps or fuzz buttons making electrical contact with the first and second plurality of electrical contacts.

Abstract: An improved vertical pin probing device is constructed with a housing with spaced upper and lower spacers of Invar®, each having a thin sheet of silicon nitride ceramic material held in a window in the spacer of adhesive. The Invar spacers may be composed of Invar foils adhered to one another in a laminated structure. The sheets of silicon nitride have laser-drilled matching patterns of holes supporting probe pins and insulating the probe pins from the housing. The Invar spacers and silicon nitride ceramic sheets have coefficients of thermal expansion closely matching that of the silicon chip being probed, so that the probing device compensates for temperature variations over a large range of probing temperatures.

Abstract: A probe head assembly for use in a vertical pin probing device of the type used to electrically test integrated circuit devices has a metallic spacer portion formed from a plurality of laminated metallic layers. The laminated metallic layers are formed from a low coefficient of thermal expansion metal, such as Invar, a 36% nickel—64% iron alloy. By orienting the metallic grains of the laminated metal layers to be off-set from the orientation of metallic grains of adjacent metallic foil layers, increased strength and flatness is achieved.