Patents Assigned to Western Digital Technologies
  • Publication number: 20240144966
    Abstract: The present disclosure generally relates to a dual free layer two dimensional magnetic recording read head. The read head comprises a first lower shield, a first sensor disposed over the first lower shield, a first upper shield disposed over the first sensor, a read separation gap (RSG) disposed on the first upper shield, a second lower shield disposed over the RSG, a second sensor disposed over the second lower shield, and a second upper shield disposed over the second sensor. In some embodiments, the second lower shield comprises a CoFeHf layer. In another embodiment, the second lower shield is a synthetic antiferromagnetic multilayer comprising a first shield layer, a second shield layer, and a CoFe/Ru/CoFe anti-ferromagnetic coupling layer or a Ru layer disposed therebetween, the first and second shield layers comprising NiFe and CoFe. In yet another embodiment, the second lower shield comprises layers of Ru, IrMn, and NiFe.
    Type: Application
    Filed: July 26, 2023
    Publication date: May 2, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Ming MAO, Chen-Jung CHIEN, Goncalo Marcos BAIÃO DE ALBUQUERQUE, Chih-Ching HU, Yung-Hung WANG, Ming JIANG
  • Publication number: 20240143227
    Abstract: A data storage device has a cache and a non-volatile memory. Instead of flushing the entire cache to the non-volatile memory in response to a command from a host, the data storage device flushes only the cached data that is associated with an identifier provided by the host. This allows the cached data associated with the identifier to be flushed more quickly. The data storage device can also prioritize queued commands that are associated with the identifier.
    Type: Application
    Filed: July 12, 2023
    Publication date: May 2, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Rotem Sela, Meytal Soffer, Asher Druck
  • Publication number: 20240144964
    Abstract: The present disclosure is generally related to a magnetic recording device comprising a magnetic recording head having a first current flow in a cross-track direction through a trailing shield. In one or more embodiments, a second current flows in a cross-track direction around the main pole. The magnetic recording device comprises a main pole disposed between a trailing shield, a leading shield, and side shields. A trailing gap is disposed between the side shields and the trailing shield. A high moment seed layer is disposed between the main pole and the trailing shield. A first insulation layer is disposed within the trailing shield and directs the first current through the trailing shield, guided to the proximity of the main pole. A second insulation layer, disposed below the trailing shield, directs the second current through the trailing shield, or alternatively through the side shields and around the main pole.
    Type: Application
    Filed: January 9, 2024
    Publication date: May 2, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Alexander GONCHAROV, Muhammad ASIF BASHIR, Petrus Antonius VAN DER HEIJDEN, Yunfei DING, Zhigang BAI, James Terrence OLSON
  • Publication number: 20240143509
    Abstract: Zoned memory typically requires write commands to be sent from a host to a data storage device in logical block address (LBA) sequential order. Instead of rejecting out-of-order write commands, the data storage device can execute those commands and internally deal with the out-of-order problem. For example, the data storage device can use a special zone logical-to-physical address table, use a temporary zone data buffer, and/or store a data's LBA in a header for later matching.
    Type: Application
    Filed: July 14, 2023
    Publication date: May 2, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Rotem Sela, Hadas Oshinsky, Einav Zilberstein
  • Publication number: 20240144965
    Abstract: The present disclosure generally relates to spin-orbit torque (SOT) devices comprising a bismuth antimony (BiSb) layer. The SOT devices further comprises a first shield, a BiSb layer disposed over the first shield (S1), a free layer (FL) disposed over the BiSb layer, and a second shield (S2) disposed over the FL. The S1, the FL, and the S2 are disposed at a media facing surface (MFS). The BiSb layer is recessed from the MFS a first distance of about 5 nm to about 20 nm. The FL has a length greater than the first distance. A notch and/or an insulation layer is disposed adjacent to the BiSb layer at the MFS. Current may be configured to flow vertically through the S2 to the FL, and horizontally from the FL to the BiSb layer. Current may be configured to flow vertically through the S2 to the S1.
    Type: Application
    Filed: July 31, 2023
    Publication date: May 2, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Quang LE, Rohan Babu NAGABHIRAVA, Xiaoyong LIU, Brian R. YORK, Cherngye HWANG, Son T. LE, Randy G. SIMMONS, Kuok San HO, Hisashi TAKANO
  • Publication number: 20240143228
    Abstract: The present disclosure generally relates to read and write operations utilizing barrier commands. Using barrier commands and a snapshot of doorbell states of submission queues (SQs), the necessary write commands to perform a read may be identified and executed to reduce any wait time of the host. As such, host delays during reads and writes are reduced. In absence of a barrier command, the host needs to wait for writes to complete before performing a read. When a barrier command is used, the host needs to wait for the barrier command to complete before performing a read. The controller will execute the post barrier reads only after completing the pre-barrier writes. As will be discussed herein, the controller completes the barrier command as soon as a doorbell snapshot is taken even though the pre-barrier writes may not yet be completed.
    Type: Application
    Filed: July 12, 2023
    Publication date: May 2, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Amir SEGEV, Shay BENISTY, Rotem SELA
  • Publication number: 20240144962
    Abstract: The present disclosure is generally related to a magnetic recording device comprising a magnetic recording head. The magnetic recording head comprises a main pole, a shield, and a spintronic device disposed between the main pole and the shield. The spintronic device comprises two field generation layers (FGLs), two spin polarization layers (SPLs), and two spin kill layers. The spintronic device further comprises one or more optional thin negative beta material layers, such as layers comprising FeCr, disposed in contact with at least one of the spin kill layers. When electric current is applied, the spin kill layers and optional negative beta material layers eliminate or reduce any spin torque between the FGLs and the SPLs.
    Type: Application
    Filed: July 25, 2023
    Publication date: May 2, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Muhammad ASIF BASHIR, Alexander GONCHAROV, Zhigang BAI, Masato SHIIMOTO, Yunfei DING
  • Publication number: 20240143337
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. When a boot operation of the data storage device is initiated, the controller retrieves a relevant boot file from the memory device to boot the data storage device with. The relevant boot file to be retrieved from a plurality of boot files may be determined by a write temperature corresponding to the temperature of when the boot file was programmed to the memory device and a read temperature of the boot file during the boot operation. Each boot file of the plurality of boot files is programmed using different programming parameters in order to cover a range of possible retention levels.
    Type: Application
    Filed: July 6, 2023
    Publication date: May 2, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Eran MOSHE, Gadi VISHNE, Refael BEN-RUBI
  • Publication number: 20240144963
    Abstract: The present disclosure is generally related to a magnetic recording device comprising a magnetic recording head. The magnetic recording head comprises a main pole, a hot seed layer, and a spintronic device disposed between the main pole and the hot seed layer. The spintronic device comprises two field generation layers (FGLs), two spin polarization layers (SPLs), and two spin kill layers. The second SPL of the spintronic device drives the second FGL. The spintronic device further comprises one or more optional thin negative beta material layers, such as layers comprising FeCr, disposed in contact with at least one of the spin kill layers. When electric current is applied, the spin kill layers and optional negative beta material layers eliminate or reduce any spin torque between the FGLs and the SPLs.
    Type: Application
    Filed: July 25, 2023
    Publication date: May 2, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Muhammad ASIF BASHIR, Alexander GONCHAROV, Zhigang BAI, Masato SHIIMOTO, Yunfei DING
  • Publication number: 20240144996
    Abstract: Technology is disclosed herein compensating for neighbor memory cell interference on a target memory cell when reading the target memory cell. The voltage that is applied to the bit line associated with the target memory cell may have a magnitude that depends on the data state of the neighbor memory cell. The magnitude of the voltage on the bit line may impact the amount of drain-induced barrier lowering (DIBL) experienced by the target memory cell. The amount of DIBL may be used to provide a desired amount of compensation for the neighbor memory cell interference. A higher bit line voltage may be used to create a greater amount of DIBL and therefore greater amount of compensation for neighbor memory cell interference.
    Type: Application
    Filed: July 21, 2023
    Publication date: May 2, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Xuan Tian, Liang Li
  • Publication number: 20240142399
    Abstract: Disclosed herein are systems for detecting molecules. In some embodiments, a system includes a multiplexer, a read amplifier coupled to the multiplexer, a digitizer coupled to the read amplifier, a first nanopore, a first sense electrode situated on a first side of the first nanopore, a first counter electrode situated on a second side of the first nanopore, a first shield at least partially surrounding the first sense electrode and coupled to the multiplexer, a first shield driver coupled to the first shield, drive circuitry coupled to the first sense electrode, and control logic coupled to the drive circuitry, the multiplexer, and to the digitizer. In some embodiments, the control logic is configured to control the drive circuitry and/or the multiplexer to select the first sense electrode and/or the first counter electrode, and obtain a digitized signal from the digitizer, the digitized signal representing a current through the first nanopore.
    Type: Application
    Filed: January 7, 2024
    Publication date: May 2, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventor: Daniel BEDAU
  • Publication number: 20240144961
    Abstract: Embodiments of the present disclosure relate to magnetic recording heads (e.g., magnetic write heads) for magnetic recording devices (e.g., hard disk drives (HDD's)). A magnetic recording head includes, in a gap between a write pole and a trailing shield: a spin polarization layer (SPL), a free layer, and a spacer layer between the SPL and free layer. A spin torque layer (STL) is additionally included, and is separated from the free layer by a barrier layer that reduces or eliminates spin torque between the free layer and the STL. In one or more embodiments, to enable a thinner barrier layer, one or more dusting layers are inserted between the write pole and the trailing shield, and the one or more dusting layers are each formed of iron-chromium (FeCr). This helps maintain a thinner or narrower material stack in the gap and enhances writer performance.
    Type: Application
    Filed: July 12, 2023
    Publication date: May 2, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Muhammad ASIF BASHIR, Alexander GONCHAROV, Petrus Antonius VAN DER HEIJDEN
  • Publication number: 20240143508
    Abstract: The present disclosure generally relates to improved address translation. Rather than fetching translated addresses using ATS/ATC, a HIM address translation search engine (HATS) is used through implementing the ATC in a layer above per an NVMe command. The HATS is an engine that will monitor pointers with untranslated addresses and will fetch the translated addresses for the pointers. Once the translated addresses are fetched for the pointer, the HATS will overwrite the untranslated address with the translated address. The HATS will then update the status of the pointers. When a translation request fails, the device will use PRI to request the translated address. During a translation request fail the device will drain any incoming requests while skipping the data transfer phase. The device will not block any other requests in a queue. Once that translated address is received through the PRI flow, the status of the pointer will be updated.
    Type: Application
    Filed: July 26, 2023
    Publication date: May 2, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Shay BENISTY, Amir SEGEV
  • Publication number: 20240144960
    Abstract: The present disclosure generally relates to a two dimensional magnetic recording (TDMR) spin-orbit torque (SOT) read head comprising bismuth antimony (BiSb) layers. The read head comprises a lower reader comprising a first SOT stack and an upper reader comprising a second SOT stack. The first SOT stack and the second SOT stack each individually comprise a BiSb layer recessed from a media facing surface (MFS) and a free layer exposed at the MFS. The BiSb layers of each SOT stack are recessed from the MFS a distance of about 5 nm to about 20 nm, the distance being less than a length of the free layers. In one embodiment, the lower reader and the upper reader share a current path. In another embodiment, the lower reader and the upper reader have separate current paths.
    Type: Application
    Filed: July 26, 2023
    Publication date: May 2, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Quang LE, Rohan Babu NAGABHIRAVA, Xiaoyong LIU, Brian R. YORK, Son T. LE, Cherngye HWANG, Kuok San HO, Hisashi TAKANO
  • Publication number: 20240143512
    Abstract: The present disclosure generally relates to improved optimization of a cache lookup operation by structuring the write cache buffers differently using a link-list. Rather than executing a read command first and then executing a write command only after the read command is executed, this disclosure suggests reordering the command executions. A device waits before executing the read command giving the opportunity to obtain the overlap write command. The device then reorders the command execution and executes first the write command and then executes the read command by accessing the write cache instead of the NAND. When two write commands need to be executed consecutively, the link-list operation is used. The controller finds the relevant buffer in the cache that is needed and overwrites the buffer with the new data. The new data is then written to the cache without accessing the cache multiple times.
    Type: Application
    Filed: July 17, 2023
    Publication date: May 2, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Shay BENISTY, Judah Gamliel HAHN
  • Patent number: 11971775
    Abstract: Various processes for efficiently and effectively determining or predicting whether data stored in a non-volatile storage device is unreadable and/or unrecoverable during a read-retry process. To make the determination, different dynamic read threshold (DRT) entries of a dynamic read threshold (DRT) table are applied, in parallel, across different planes of the non-volatile storage device to determine whether the data is unreadable and/or unrecoverable.
    Type: Grant
    Filed: September 16, 2022
    Date of Patent: April 30, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Yogendra Singh Sikarwar, Prateek Kumar TR
  • Patent number: 11972118
    Abstract: A mobile data storage device (DSD) incorporating a mobile data storage device (DSD), the mobile DSD comprising a non-volatile storage medium configured to store user data, a data path configured to transmit at least data between the mobile DSD and a host computer system, a housing having a machine readable optical code and a controller. The controller is configured to receive, from the data path, a request to restore the mobile DSD to factory settings. The controller also receives, from the data path, a unique access passcode derived from the machine readable optical code. The controller validates the unique access passcode, and, in response to determining that the unique access passcode is valid, restores the mobile DSD to factory settings.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: April 30, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Alexander Lemberg, Rotem Sela, Noam Even-Chen, Asher Druck
  • Patent number: 11972035
    Abstract: Aspects of a storage device including a memory and a controller are provided. The controller can receive a data stream from a host device, the data stream indicating a plurality of encryption keys associated with the data stream, and segregate the data stream into a plurality of data stream portions based on the plurality of encryption keys. The controller can encode the plurality of data stream portions into a plurality of encoded data stream portions with the plurality of encryption keys. The controller also can generate a mapping indicating an association between each of the plurality of encryption keys with a respective one of the plurality of encoded data stream portions. Thus, the controller may store the plurality of encoded data stream portions and the plurality of encryption keys in the memory based on the mapping, thereby improving security access to data stored in the storage device.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: April 30, 2024
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Ramanathan Muthiah
  • Patent number: 11971771
    Abstract: Systems and methods for peer data storage device messaging over a control bus for power management are disclosed. Storage devices may include a host interface configured to connect to a host system and a control bus interface to connect to a control bus. Peer data storage devices may establish peer communication through the control bus interface, determine a power state, receive a power change indicator from a peer data storage device, and initiate a change in their power state. The peer data storage devices may manage their collective power as a power pool and increase or decrease power use without host intervention.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: April 30, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Eran Moshe, Danny Berler
  • Patent number: 11972149
    Abstract: A storage system is provided that performs a defragmentation operation or proactive garbage collection in its memory based on a command from a host. The command specifies which blocks in the memory should take part in the defragmentation operation by specifying a maximum amount of valid data that a block can have to qualify for defragmentation. That way, the storage system only performs defragmentation on those blocks that meet the validity criteria provided by the host. This can help improve performance of the storage system while reducing the degree of negative tradeoffs that may come with defragmentation or proactive garbage collection.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: April 30, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Einav Zilberstein, Nadav Sober, Omer Katz