Patents Assigned to Western Digital Technologies, Inc.
  • Patent number: 11606206
    Abstract: Disclosed herein is a data storage device comprising a data path and an access controller. The access controller generates a recovery private key, generates encrypted authorization data based on the recovery private key, stores the encrypted authorization data, and sends the recovery private key to a manager device. When recovery is desired, access controller receives a recovery public key, calculated based on the recovery private key, from a recovery manager device, decrypts the encrypted authorization data based on the recovery public key, generates a challenge for the recovery manager device based on the decrypted authorization data, sends the challenge to the recovery manager device over the communication channel that is different from the data path, receives a response to the challenge from the recovery manager device over the communication channel, and based at least partly on the response, enables decryption of the encrypted user content data.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: March 14, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Brian Edward Mastenbrook, Matthew Harris Klapman, Michael William Webster
  • Patent number: 11599481
    Abstract: An apparatus includes a non-volatile memory media and a storage controller. The storage controller is configured to fetch a storage command from a submission queue of a host. The submission queue has a submission queue identifier (SQID). The storage controller then determines a submission queue fetch error in response to receiving a Transport Layer Packet (TLP) error as a result of fetching the storage command. Next, the storage controller is configured to determine a command identifier (CID) for the storage command associated with the submission queue fetch error. The storage controller then sends a completion message to the host. The completion message uniquely identifies the storage command of the submission queue associated with the submission queue fetch error using the SQID and CID.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: March 7, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventor: Shay Benisty
  • Patent number: 11599298
    Abstract: A storage system erases blocks of memory prior to writing data to the blocks. Instead of erasing the blocks at the time the write operations are executed, the storage system pre-erases the blocks, which can improve performance. However, because program failure errors can occur if the blocks sit empty for a relatively-long period of time prior to programming, the storage system pre-erases the blocks upon a prediction that a host will send sequential write commands to the storage system that will use the blocks. Additionally or alternatively, the storage system can pre-erase a block upon determining that the number of write commands in a command queue in the storage system is above a threshold that represents a number of write commands needed to fill the block with data.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: March 7, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sabith Ali B N, Lakshmi Sowjanya Sunkavelli, Silky Mohanty, Noor Mohamed A A
  • Patent number: 11599505
    Abstract: By way of example, a data storage system may comprise, a non-transitory storage device storing data blocks in chunks, and a storage logic coupled to the non-transitory storage device that manages storage of data on the storage device. The storage logic is executable to receive a data stream for storage in a non-transitory storage device, the data stream including one or more data blocks, analyze the data stream to determine a domain, retrieve a pre-configured reference set based on the domain, and deduplicate the one or more data blocks of the data stream using the pre-configured reference set.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: March 7, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ashish Singhai, Ashwin Narasimha, Vijay Karamcheti, Tanay Goel
  • Patent number: 11601141
    Abstract: Apparatuses, systems, and methods are presented for error correction based on physical characteristics for memory. A controller may be configured to read a set of encoded bits from a set of cells of a memory array. The controller may be configured to divide the encoded bits into reliability groups based on one or more persistent physical characteristics associated with cells of the set of cells. The controller may be configured to provide reliability estimates based on the reliability groups to a soft decision decoder for decoding the encoded bits.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: March 7, 2023
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Gadi Vishne, David Rozman, Alex Bazarsky
  • Patent number: 11600294
    Abstract: Magnetic media including a magnetic recording layer structure formed of alternating magnetic recording sublayers and non-magnetic exchange control sublayers. The magnetic recording layer structure may include at least one magnetic recording sublayer formed to include a pair of thin films, with the films having different concentrations of platinum, ruthenium, and/or oxide segregants. That is, the sublayer has a “dual layer” structure. The dual layer structure can provide a gradient in magnetic anisotropy, saturation magnetization, and/or intergranular magnetic exchange coupling across the sublayer. In some examples, the film nearer to the substrate of the magnetic media has a higher platinum concentration than the other film. In one aspect, the magnetic media includes the substrate and the magnetic recording layer structure on the substrate, with the structure including six magnetic recording sublayers. In another aspect, a method of fabricating magnetic media with such structures is provided.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: March 7, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventor: Kai Tang
  • Patent number: 11599305
    Abstract: A data storage device configured to access a magnetic tape comprising a plurality of data tracks is disclosed, wherein the data storage device comprises at least one head configured to access the magnetic tape. A mapping table is generated having a predetermined number of segment entries per data track, wherein each segment entry corresponds to a data segment of the data track, each segment entry comprises a first logical address corresponding to a first logical data block stored in the corresponding data segment, and at least one of the data segments stores multiple logical data blocks. A target segment entry in the mapping table corresponding to a logical address of a read command is located, and the head is positioned at a beginning of a target data segment of a target data track corresponding to the target segment entry in order to execute the read command.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: March 7, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventor: Robert L. Horn
  • Patent number: 11601656
    Abstract: A method and apparatus for video processing on a data storage device. A chip bound architecture includes a CMOS coupled to one or more NAND die, the CMOS including one or more processors, memories, and error correction code (ECC) engines capable of processing video data. According to certain embodiments, macroblocks are correlated between two I-frames, including motion vectors to define different locations of correlated macroblocks. A P-frame may be determined from a previous I-frame and its correlated macroblocks and motion vectors, while a B-frame may be determined from two or more adjacent I-frames with concomitant macroblocks and motion vectors, as well as P-frames associated with an adjacent I-frame.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: March 7, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Alon Marcu, Ofir Pele, Ariel Navon, Shay Benisty, Karin Inbar, Judah Gamliel Hahn
  • Patent number: 11599304
    Abstract: The present disclosure generally relates to efficient data transfer management of zone-append commands for a zoned namespace (ZNS). The ZNS storage device comprises a memory device having a plurality of memory dies, and a controller coupled to the memory device The controller receives a plurality of zone append commands, each zone append command being associated with a zone identification identifying a zone of a plurality of zones, and fetches and aggregates data associated with each zone append command by the zone identification in an append write buffer. The aggregated data is written to the memory device upon the aggregated data for each zone reaching a predetermined programming chunk size, or to a temporary buffer if the predetermined write size is not met. Each zone uses a separate channel when sending the aggregated data for programming to the memory device, allowing multiple channels to be utilized in parallel.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: March 7, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Karin Inbar, Shay Benisty
  • Patent number: 11599277
    Abstract: A storage system determines that it is undergoing intensive reads by a host, which can occur, for example, when the storage system is being used to play a video game for a prolonged period of time. As performing a conventional read scrub operation in that situation can result in a decrease in performance, the storage system can instead use a targeted read scrub operation to reduce the impact on host read performance. The targeted read scrub operation can take the form, for example, of a periodic read scan on areas of the memory that are not part of the intensive host read, random read scans on neighboring wordlines where only a single state is read, and/or a passive read scan where acceptable but risky pages are marked for relocation.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: March 7, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Niles Yang, Nan Lu, Piyush A. Dhotre
  • Patent number: 11598828
    Abstract: The present disclosure generally relates to a Wheatstone bridge array that has four resistors. Each resistor includes a plurality of TMR structures. Two resistors have identical TMR structures. The remaining two resistors also have identical TMR structures, though the TMR structures are different from the other two resistors. Additionally, the two resistors that have identical TMR structures have a different resistance area as compared to the remaining two resistors that have identical TMR structures. Therefore, the working bias field for the Wheatstone bridge array is non-zero.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: March 7, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Yuankai Zheng, Christian Kaiser, Zhitao Diao, Chih-Ching Hu, Chen-jung Chien, Yung-Hung Wang, Dujiang Wan, Ronghui Zhou, Ming Mao, Ming Jiang, Daniele Mauri
  • Patent number: 11599283
    Abstract: Techniques are described for reducing power consumption in a distributed data storage system using a hierarchy rule that is generated based on a spreading policy and a set of tolerable failures. A method may operate to distribute erasure-encoded data of a first data object across first and second portions of a distributed storage system using a hierarchy rule corresponding to a spreading policy based on a set of tolerable failures from which the first data object can be recovered. The method disables the first portion of the distributed storage system that includes a first portion of the erasure-encoded data. The first portion of the distributed storage system is determined according to the spreading policy and the hierarchy rule identifies the set of tolerable failures.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: March 7, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventor: Stijn Blyweert
  • Patent number: 11600293
    Abstract: A magnetic recording device includes a main pole, a coil around the main pole, a trailing shield, and a leading shield. A trailing gap is between the main pole and the trailing shield. In one embodiment, the trailing gap includes a non-magnetic conductive material. In another embodiment, the trailing gap includes a spin torque oscillator device. A leading gap is between the main pole and the leading shield. The leading gap includes a non-magnetic conductive material. The main pole is coupled to a first terminal. The trailing shield coupled to a second terminal. The leading shield is coupled to a third terminal.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: March 7, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Terence Lam, Michael Kuok San Ho, Yaguang Wei, Zhigang Bai, Muhammad Asif Bashir
  • Publication number: 20230067236
    Abstract: The present disclosure generally relates to searching an overlap table for data requested to be read in a plurality of read commands received. Rather than searching the table for data corresponding to each command individually, the searching occurs for the plurality of commands in parallel. Furthermore, the overlap table can comprise multiple data entries for each line. The number of read commands can be accumulated prior to searching, with the accumulating being a function of a queue depth permitted by the host device. Parallel searching of the overlap table reduces the average search time.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Shay BENISTY, Amir SEGEV
  • Publication number: 20230062493
    Abstract: A storage system determines that it is undergoing intensive reads by a host, which can occur, for example, when the storage system is being used to play a video game for a prolonged period of time. As performing a conventional read scrub operation in that situation can result in a decrease in performance, the storage system can instead use a targeted read scrub operation to reduce the impact on host read performance. The targeted read scrub operation can take the form, for example, of a periodic read scan on areas of the memory that are not part of the intensive host read, random read scans on neighboring wordlines where only a single state is read, and/or a passive read scan where acceptable but risky pages are marked for relocation.
    Type: Application
    Filed: September 2, 2021
    Publication date: March 2, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Niles Yang, Nan Lu, Piyush A. Dhotre
  • Patent number: 11595463
    Abstract: A data storage system including a data storage device located on a first network and configured to download data from a network site based on universal resource locator (“URL”) information of the network site, and an electronic device located on a second network different than the first network. The electronic device determines the URL information of the network site, receives user authentication data, receives a network address of the data storage device from a server using the user authentication data, and transmits the URL information to the data storage device using the network address of the data storage device. This causes the data storage device to download data from the network site contingent on correct user authentication being provided.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: February 28, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventor: Dean M. Jenkins
  • Patent number: 11593198
    Abstract: Systems and methods for storing data are described. A system can comprise a controller, one or more physical non-volatile memory devices, a bus comprising a plurality of input/output (I/O) lines. The controller configured to receive data, encode the received data into a codeword, and transfer, in parallel, different portions of the codeword to different physical non-volatile memory devices among the plurality of physical non-volatile memory devices.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: February 28, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Shemmer Choresh, Tomer Tzvi Eliash
  • Patent number: 11594247
    Abstract: Disclosed herein are sliders with at least one notch-cut in the trailing pad, methods of making them, and data storage devices comprising them. In some embodiments, a slider comprises a leading-edge surface, a trailing-edge surface, and an air-bearing surface (ABS) that includes a trailing pad situated closer to the trailing-edge surface than to the leading-edge surface, wherein the trailing pad comprises at least one notch-cut (e.g., two notch-cuts) in a trailing side of the trailing pad. The at least one notch-cut provides higher pressure at the recording head situated in the trailing pad and higher thermal flight control efficiency without a commensurate increase in touch-down power. As a result, the temperature around the recording head is lower than without the at least one notch-cut, thereby improving the lifetime of the recording head and data storage device.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: February 28, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Biao Sun, Weidong Huang
  • Patent number: 11593520
    Abstract: A method and apparatus for enforcing privacy within one or more memories of a data storage system are disclosed. In one embodiment, sensor data containing personally identifiable information (PII) is provided to a memory. In some embodiments, the memory of disclosed systems and methods may be volatile, non-volatile, or a combination. Within the memory, PII is detected in some embodiments by AI-based computer vision, voice recognition, or natural language processing methods. Detected PII is obfuscated within the memory prior to making the sensor data available to other systems or memories. In some embodiments, once PII has been obfuscated, the original sensor data is overwritten, deleted, or otherwise made unavailable.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: February 28, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Judah Gamliel Hahn, Ariel Navon, Shay Benisty
  • Patent number: 11593204
    Abstract: An approach to identifying a corrective action for a data storage device (DSD), such as one implemented in a fleet of DSDs in a data center, involves receiving error data about excursions from normal operational behavior of the DSD, inputting data representing a particular excursion into a probabilistic decision network which characterizes a set of DSD operational metrics and certain DSD controller rules that represent internal controls of the DSD and corresponding conditional relationships among the operational metrics, determining from the decision network the likelihood that one or more possible causes was a contributing factor to the particular excursion, and determining a corrective action for the particular excursion based on the determined likelihood of a particular cause of the one or more possible causes. The corrective action may then be shared with the DSD for in-situ execution of corresponding self-repair operations.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: February 28, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Bernd Lamberts, Jeffrey Hobbet, Maulik Thaker, Evan Richardson, Remmelt Pit