Patents Assigned to Western Digital Technology, Inc.
  • System and method for performing discriminative predictive read
    Patent number: 11010299
    Abstract: Systems and methods for pre-fetching data in a memory device are disclosed. The method may include receiving a current read command and determining whether the current read command is a random read command, for example based on a data chunk length identified by the current read command. The method may further include updating a prior read command data structure with the current read command, for random read commands; determining a predicted next read command from the prior read command data structure based on the current read command; and pre-fetching data associated with the predicted next read command. Functionality for prediction of next read commands, or pre-fetch of predicted next read commands, may be turned on or off based on resource availability or prediction success rate measurements.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: May 18, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ariel Navon, Eran Sharon, Idan Alrod
  • Adjustable performance parameters for SSDs
    Patent number: 11010074
    Abstract: Disclosed is a system and method for providing host adjustable performance parameters for SSDs. The method includes accessing a latency profile based on a determined device age of a solid state drive (SSD). The method also includes providing for display a user interface comprising a plurality of interface elements to adjust a respective plurality of performance specifications of the SSD, wherein the user interface is configured based on the latency profile. The method also includes receiving, via the user interface, an adjustment to the plurality of performance specifications. The method also includes sending an instruction to the SSD to configure the SSD with a parameter set based on the adjusted plurality of performance specifications.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: May 18, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Navneeth Kankani, Linh Tien Truong
  • Multi-level loop cut process for a three-dimensional memory device using pitch-doubled metal lines
    Patent number: 11011581
    Abstract: First elongated loop-shaped conductive material portions are formed over a substrate. A two-dimensional array of memory pillar structures is formed over the first elongated loop-shaped conductive material portions. Second elongated loop-shaped conductive material portions over the two-dimensional array of memory pillar structures. Each of the elongated loop-shaped conductive material potions includes a respective pair of line segments and a respective pair of end segments adjoined to ends of the respective pair of line segments. A moat trench that at least partially laterally encloses the two-dimensional array of memory pillar structures can be formed by performing an anisotropic etch process that removes parts of the first and second elongated loop-shaped conductive material portions, thereby separating each loop-shaped conductive material portion into two disjoined line segments.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: May 18, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Yuji Takahashi, Jo Sato, Wei Kuo Shih
  • Data storage device executing access commands based on leapfrog sort
    Patent number: 11010099
    Abstract: A data storage device is disclosed comprising a head actuated over a non-volatile storage medium. A plurality of access commands are received from a host and sored in a host queue and a pending queue. A first access command is selected from the host queue, wherein the first access command having a first execution time needed to execute the first access command. When a second access command in the pending queue can be executed within the first execution time, the second access command is executed, and after executing the second access command, the first access command in the host queue is executed. After selecting the first access command from the host queue, a third access command is transferred from the pending queue to the host queue based on a first-in-first-out (FIFO) order of the pending queue.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: May 18, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventor: David R. Hall
  • Method and system for managing memory device
    Patent number: 11010239
    Abstract: The subject technology provides for managing a data storage system. A data operation error for a data operation initiated in a first non-volatile memory die of a plurality of non-volatile memory die in the data storage system is detected. An error count for an error type of the data operation error for the first non-volatile memory die is incremented. The incremented error count satisfies a first threshold value for the error type of the data operation error is determined. The first non-volatile memory die is marked for exclusion from subsequent data operations.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: May 18, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sanghoon Chu, Scott Jinn, Yuriy Pavlenko, Kum-Jung Song
  • Distributed batch processing of non-uniform data objects
    Patent number: 11010103
    Abstract: The described methods, systems, and other aspects can advantageously provide balanced multi-stage processing of non-uniform object data. An example method may receive a list of buckets. Each of the buckets in the list of buckets can store one or more restorable objects. The method further comprises distributing the list of buckets to the two or more second nodes; determining a number of the one or more restorable objects in each bucket; determining a size of the one or more restorable objects in each bucket; generating batches of to-be-restored data objects based on the determined number of the one or more restorable objects in each bucket and the determined size of the one or more restorable objects in each bucket; and distributing the batches among the two or more second nodes for storage-related task processing.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: May 18, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ameet Pyati, Souvik Roy, Tomy Ammuthan Cheru, Muhammad Tanweer Alam
  • Apparatus and method for using fields in N-space translation of storage requests
    Patent number: 11010075
    Abstract: A translation system can translate a request having multiple fields to a physical address using the fields as indexes to a multi-dimensional graph. A field or portion of a field can represent a location along an axis. When combined together, the fields can represent a point in n-space, where n is the number of axes. In some embodiments, a nearest neighbor calculation can be sufficient along an axis. Therefore, a point in n-space defined by the fields can be translated along an axis until a nearest neighbor entry is determined. When the entry is determined, the entry can be accessed to determine a correct response to the translation request.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: May 18, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Radoslav Danilak, Ladislav Steffko, Qi Wu
  • Universal serial bus voltage reducing adaptor
    Patent number: 11010326
    Abstract: A method and apparatus are provided to receive a voltage at a first value at a voltage reducing adaptor, ascertain a voltage supply requirement for the memory arrangement to obtain and ascertained voltage supply requirement, reduce the voltage from the first value to the ascertained voltage supply requirement within the adaptor and supply the voltage at the ascertained voltage supply requirement to the memory arrangement.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: May 18, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Charles Neumann, Robert P. Ryan
  • Embedding protocol parameters in data streams between host devices and storage devices
    Patent number: 11003614
    Abstract: A method includes receiving, by a storage device and from a host device, a set of protocol parameters initialized by the host device. The set of protocol parameters are used to facilitate data transfer between the host device and the storage device. The method also includes determining that a threshold value associated with the data transfer between the host device and the storage device has been satisfied. The method further includes, in response to determining that the threshold value has been satisfied, sending, by the storage device and to the host device, the set of protocol parameters that were received from the host device.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: May 11, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Adam Espeseth, Colin Christopher McCambridge
  • Magnetoresistive memory device including a high dielectric constant capping layer and methods of making the same
    Patent number: 11005034
    Abstract: Magnetoelectric or magnetoresistive memory cells include at least one of a high dielectric constant dielectric capping layer and/or a nonmagnetic metal dust layer located between the free layer and the dielectric capping layer.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: May 11, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Bhagwati Prasad, Matthew Carey, Alan Kalitsov, Bruce Terris
  • Systems and methods for managing physical-to- logical address information
    Patent number: 11003373
    Abstract: A method for managing physical-to-logical address information in a memory system includes determining whether a memory fragment of a memory block is a last memory fragment of the memory block. The method also includes, in response to a determination that the memory fragment is not the last memory fragment of the memory block: performing a write operation on the memory fragment; storing, in cache associated with the memory system, physical-to-logical address information associated with the memory fragment; and, in response to a determination that the cache is full, writing, to a next memory fragment of the memory block, control metadata associated with physical-to-logical address information stored in the cache.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: May 11, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Niraj Srimal, Ramanathan Muthiah
  • Perpendicular spin transfer torque MRAM memory cell with in-stack thermal barriers
    Patent number: 11004489
    Abstract: A perpendicular spin transfer torque MRAM memory cell includes a magnetic tunnel junction stack comprising a pinned layer having a fixed direction of magnetization, a free layer having a direction of magnetization that can be switched, a tunnel barrier between the pinned layer and the free layer, a cap layer above the free layer and one or more in-stack multi-layer thermal barrier layers having multiple internal interfaces between materials. The thermal barrier layers have high enough thermal resistivity to maintain the heat generated in the memory cell and low enough electrical resistivity to not materially change the electrical resistance of the memory cell. One embodiment further includes a thermal barrier liner surrounding the free layer, pinned layer, tunnel barrier and cap layer.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: May 11, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Goran Mihajlovic, Tiffany Santos, Michael Grobis
  • Combined data and control for multi-die flash
    Patent number: 11003387
    Abstract: An arrangement for providing a combined data and control signal for a multi die flash, comprising, a memory arrangement, the memory arrangement comprising at least two dies, a controller configured to send and receive signals to the memory arrangement and a common line connected to the memory arrangement and the controller and configured to transmit the signals from the controller to the at least two dies, wherein the arrangement is configured to provide a combined data and combined control signals to the multi-die flash.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: May 11, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Yoav Markus, Alexander Bazarsky
  • ITERATIVE DECODER PERFORMANCE PREDICTION USING MACHINE LEARNING
    Publication number: 20210135688
    Abstract: An illustrative embodiment of this disclosure is an apparatus, including a memory, a processor in communication with the memory, and a decoder. The processor is configured to train a classifier, calculate one or more features of a codeword, predict an outcome of decoding the codeword with the decoder, and determine, using the classifier, whether the outcome satisfies a predetermined threshold. In some embodiments, based on the outcome, the processor selects a set of decoder parameters to improve decoder performance.
    Type: Application
    Filed: November 5, 2019
    Publication date: May 6, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Ran Zamir, David Avraham, Eran Sharon
  • Enabling high speed command address interface for random read
    Patent number: 10997097
    Abstract: A memory device includes a memory controller to transmit or receive input/output (“I/O”) data via an I/O signal, as well as transmit command data, address data, or parameter data via another signal in parallel with transmitting or receiving the I/O data. The memory device also includes a memory module communicably coupled to the memory controller. The memory module receives the command data, address data, or parameter data from the memory controller to perform an operation.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: May 4, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sneha Bhatia, Vinayak Ghatawade
  • Adaptive read trim for second read data retention
    Patent number: 10996862
    Abstract: A data storage system performs operations including determining an endurance level of a block of memory cells; adjusting a read performance profile for the block of memory cells based on the determined endurance level; receiving a data read command specifying data to be read from a particular memory cell of the block of memory cells; and in response to the data read command, performing a read operation on the particular memory cell using the adjusted read performance profile.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: May 4, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Phil Reusswig, Mohsen Purahmad, Sahil Sharma, Rohit Sehgal, Niles Yang
  • Calibrating non-volatile memory read thresholds
    Patent number: 10998041
    Abstract: In a read scan operation, a first read level window is scanned for a first candidate read level that activates the fewest number of memory cells in relation to other candidate read levels within that window. A second read level window for a second candidate read level is then configured based on a correlation between at least one of the two adjacent memory states and one or more other adjacent memory states associated with the second read level window. The second read level window is scanned for a second candidate read level that activates the fewest number of memory cells, or results in the fewest bit errors, in relation to other candidate read levels within the second read level window. Next, a read operation is configured to use the first candidate read level and the second candidate read level.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: May 4, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Dudy Avraham, Alex Bazarsky, Rotem Feinblat, David Rozman
  • Spin orbital torque via spin hall effect based energy assisted magnetic recording
    Patent number: 10997991
    Abstract: A magnetic recording head includes a trailing shield, a main pole, and a spin Hall layer. The spin Hall layer is disposed between the trailing shield and the main pole. A first spin torque layer is disposed between the spin Hall layer and the trailing shield. A second spin torque layer is disposed between the spin Hall layer and the main pole.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: May 4, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Suping Song, Zhanjie Li, Terence Lam, Lijie Guan
  • Data storage device compensating for mode hop of a laser
    Patent number: 10997997
    Abstract: A data storage device is disclosed comprising a head actuated over a recording medium, wherein the head comprises a laser configured to heat the recording medium. A mode hop map is generated for a write power applied to the laser during a write operation. The write power is applied to the laser during the write operation and the write power is adjusted in response to the mode hop map.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: May 4, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventor: Shaomin Xiong
  • Spin-torque oscillator with multilayer seed layer between the write pole and the free layer in a magnetic recording write head
    Patent number: 10997993
    Abstract: A magnetic recording write head and system has a spin-torque oscillator (STO) located between the write head's write pole and trailing shield. The STO's ferromagnetic free layer is located near the write pole with a multilayer seed layer between the write pole and the free layer. The STO's nonmagnetic spacer layer is between the free layer and the STO's ferromagnetic polarizer. The polarizer may be the trailing shield of the write head, one or more separate polarizer layers, or combinations thereof. The STO electrical circuitry causes electron flow from the write pole to the trailing shield. The multilayer seed layer removes the spin polarization of electrons from the write pole, which enables electrons reflected from the polarizer layer to become spin polarized, which creates the spin transfer torque on the magnetization of the free layer. The multilayer seed layer includes a Mn or a Mn-alloy layer.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: May 4, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: James Mac Freitag, Zheng Gao, Masahiko Hashimoto, Sangmun Oh