Abstract: A computer system based on wafer-on-wafer architecture is provided, comprising a memory device and a logic circuit layer stacked in a wafer on wafer structural configuration. The memory device comprises a memory array and a circuit driver. The memory array comprises a shared circuit path and a plurality of memory cells, wherein the shared circuit path is connected to the memory cells. The circuit driver is connected to the shared circuit path, driving the memory cells. The logic circuit layer comprises a plurality of bonding pads for signal transmission, and a latency controller, connected to the memory array through the bonding pads, adjusting the number of memory cells connecting the shared circuit path, thereby dynamically adjusting the latency characteristics of the memory array. Embodiments of the memory device and the memory control method are also provided.

Abstract: A computer system configured to overcome the conventional bottleneck of memory throughput. A wafer-on-wafer (WOW) technology is adapted to overcome the physical limitation of quantity and length in circuit deployments. The memory devices and the memory controllers in the logic circuit layer are improved to transmit data in differential signals. The differential signals can significantly reduce the error rate in high-speed transmissions, at a voltage level far lower than that of the conventional single-end signals. Thus, the power consumption of the computer system is significantly reduced. Furthermore, the memory controller in the computer system is improved to be an integrated controller having control over physical layer signals. Thereby, the conventional physical layer interface is no longer needed in the computer system, and therefore the cost to the computer system is further reduced.

Abstract: A computer system based on wafer-on-wafer architecture is provided, comprising a memory device and a logic circuit layer stacked in a wafer on wafer structural configuration. The memory device comprises a memory array and a circuit driver. The memory array comprises a shared circuit path and a plurality of memory cells, wherein the shared circuit path is connected to the memory cells. The circuit driver is connected to the shared circuit path, driving the memory cells. The logic circuit layer comprises a plurality of bounding pads for signal transmission, and a latency controller, connected to the memory array through the bounding pads, adjusting the number of memory cells connecting the shared circuit path, thereby dynamically adjusting the latency characteristics of the memory array. Embodiments of the memory device and the memory control method are also provided.

Abstract: A computer system configured to overcome the conventional bottleneck of memory throughput. A wafer-on-wafer (WOW) technology is adapted to overcome the physical limitation of quantity and length in circuit deployments. The memory devices and the memory controllers in the logic circuit layer are improved to transmit data in differential signals. The differential signals can significantly reduce the error rate in high-speed transmissions, at a voltage level far lower than that of the conventional single-end signals. Thus, the power consumption of the computer system is significantly reduced. Furthermore, the memory controller in the computer system is improved to be an integrated controller having control over physical layer signals. Thereby, the conventional physical layer interface is no longer needed in the computer system, and therefore the cost to the computer system is further reduced.