Abstract: The various embodiments herein provide a method and a system for providing a bus transaction monitoring and debugging using FPGA. The system comprises a first FPGA, a second FPGA, application software and a communication interface to connect the second FPGA with the application software. The second FPGA comprises a monitor RTL for tapping data signals from different levels of the first FPGA, a transaction based signal trigger for capturing the signals tapped at different levels of the RTL, a monitor data interface for storing the data signals of interest and a packetizer for converting the signals to a plurality of data packets and transmit the data packets to the application software. The application software decodes the transmitted data packets and displays the transactions on a waveform viewer by communicating the information related to the data packets using a plurality of communication protocols.

Abstract: The various embodiments herein provide a method and a system for creating a verification plan in executable structure for verifying a product specification using a web user interface. The method comprises collecting the input parameters through a web user interface. The input parameters are stored in a temporary storage are converted to an object with a format such as XML. An interconnected structure of the related objects is created and transformed into a plurality of complex objects for generating a plurality of features. The stored information is fetched and processed by inserting the structure values into a permanent file based on header tag to identify an object. An output for the processed information is generated and displayed through the web user interface. The milestones of the product are directly mapped to the features for generating the features of the product.

Abstract: The various embodiments of the present invention provide a method and system for providing random sequence coverage. The method comprising receiving a plurality of data packet packets carrying transaction data from a transaction database, specifying transactions in a configuration file along with the transaction data, identifying one or more fields in the packets received from the transaction database, generating an automatic random sequence based on the identification of at least one of a field among the one or more fields in the data packets, generating a coverage report for the random sequence generated automatically and determining uncovered sequences based on the coverage report generated.

Abstract: The various embodiments of the present invention provide a method and system for providing random sequence coverage. The method comprising receiving a plurality of data packet packets carrying transaction data from a transaction database, specifying transactions in a configuration file along with the transaction data, identifying one or more fields in the packets received from the transaction database, generating an automatic random sequence based on the identification of at least one of a field among the one or more fields in the data packets, generating a coverage report for the random sequence generated automatically and determining uncovered sequences based on the coverage report generated.

Abstract: The various embodiments herein provide a method and a system for providing a bus transaction monitoring and debugging using FPGA. The system comprises a first FPGA, a second FPGA, application software and a communication interface to connect the second FPGA with the application software. The second FPGA comprises a monitor RTL for tapping data signals from different levels of the first FPGA, a transaction based signal trigger for capturing the signals tapped at different levels of the RTL, a monitor data interface for storing the data signals of interest and a packetizer for converting the signals to a plurality of data packets and transmit the data packets to the application software. The application software decodes the transmitted data packets and displays the transactions on a waveform viewer by communicating the information related to the data packets using a plurality of communication protocols.

Abstract: The various embodiments of the present invention provide a method for automatically generating a unique set of test vectors for verifying design intent of integrated circuit chips. The method includes obtaining configuration parameters associated with a plurality of integrated circuit chips, generating an Executable Verification Plan pertaining to the configuration parameters of a plurality of integrated circuit chips in one or more execution PCs (EPs), creating a plurality of data structures corresponding to the configuration parameters, communicating the data structures created to a DCMS server, mapping the data structures of the Execution PCs with one or more data structures present in a database of the DCMS server, customizing the executable verification plan based on changes in the configurations of the integrated circuit chips, generating a unique set of test vectors based on mapping of the data structures and performing automatic design verification of the plurality of integrated circuit chips.

Abstract: The various embodiments herein provide a method and a system for creating a verification plan in executable structure for verifying a product specification using a web user interface. The method comprises collecting the input parameters through a web user interface. The input parameters are stored in a temporary storage are converted to an object with a format such as XML. An interconnected structure of the related objects is created and transformed into a plurality of complex objects for generating a plurality of features. The stored information is fetched and processed by inserting the structure values into a permanent file based on header tag to identify an object. An output for the processed information is generated and displayed through the web user interface. The milestones of the product are directly mapped to the features for generating the features of the product.