Patents Assigned to WIN Semiconductor Corp.
  • Patent number: 10727741
    Abstract: An acoustic wave filter having thermal sensing acoustic wave resonator comprises a substrate, a plurality of series acoustic wave resonators formed on the substrate, at least one shunt acoustic wave resonator formed on the substrate and a thermal sensing acoustic wave resonator. The thermal sensing acoustic wave resonator is one of a series acoustic wave resonator and a shunt acoustic wave resonator. Thereby the thermal sensing acoustic wave resonator plays dual roles of thermal sensing and acoustic wave filtering.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: July 28, 2020
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Re Ching Lin, Shu Hsiao Tsai, Cheng Kuo Lin, Fan Hsiu Huang, Chih-Feng Chiang, Tung-Yao Chou
  • Patent number: 10720390
    Abstract: An ohmic metal for GaN device comprises a diffusion barrier seed metal layer and a plurality of metal layers. The diffusion barrier seed metal layer is formed on an epitaxial structure layer. The diffusion barrier seed metal layer is made of Pt. The epitaxial structure layer is made of AlGaN or GaN. The plurality of metal layers is formed on the diffusion barrier seed metal layer. The plurality of metal layers comprises a first metal layer and a second metal layer. The first metal layer is formed on the diffusion barrier seed metal layer. The first metal layer is made of Ti. The second metal layer is formed on the first metal layer. The second metal layer is made of Al. By the diffusion barrier seed metal layer, so as to suppress the diffusion of the plurality of metal layers into the epitaxial structure layer.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: July 21, 2020
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Chang-Hwang Hua, Yi-Wei Lien
  • Patent number: 10714409
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate; an active circuit portion, disposed on the substrate; a dielectric portion, disposed on the active circuit portion, wherein a hole is formed within the dielectric portion and the hole penetrates through the dielectric portion; and a radiating metal sheet, disposed on the dielectric portion; wherein the active circuit portion and the radiating metal sheet are coupled through the hole.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: July 14, 2020
    Assignee: WIN Semiconductors Corp.
    Inventors: Chih-Wen Huang, Jui-Chieh Chiu
  • Patent number: 10679924
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate; an active circuit portion including at least an active component and formed on a topside of the semiconductor device; and a radiating metal sheet formed on a backside of the semiconductor device. A hole is formed within the substrate and the hole penetrates through the substrate. The active circuit portion and the radiating metal sheet are coupled through the hole.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: June 9, 2020
    Assignee: WIN Semiconductors Corp.
    Inventors: Chih-Wen Huang, Jui-Chieh Chiu
  • Patent number: 10665555
    Abstract: A transition structure disposed in a package is disclosed. The transition structure comprises a first ground lead and a second ground lead; and a signal lead, disposed between the first ground lead and the second ground lead, wherein the first ground lead and the second ground lead have an exterior edge and an interior edge, the signal lead is coupled to a metal line formed on a printed circuit board (PCB) and a signal terminal of the die within the package; wherein an exterior gap formed between the first ground lead and the second ground lead at the exterior edge is wider than an interior gap formed between the first ground lead and the second ground lead at the interior edge.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: May 26, 2020
    Assignee: WIN Semiconductors Corp.
    Inventors: Jui-Chieh Chiu, Chih-Wen Huang, Chen-Yang Hsieh, You-Cheng Lai
  • Patent number: 10656178
    Abstract: A method for aligning an inhomogeneous receiver with an anisotropic emitter on a wafer probing system, wherein a reference semiconductor die comprising a reference pad and an anisotropic emitter is formed on a semiconductor wafer, the reference pad is located at a reference-pad-and-anisotropic-emitter relative position corresponding to the anisotropic emitter, the method comprises following steps of: measuring a receiver center position of an inhomogeneous receiver configured on a wafer probing system by a profile sensor; measuring a reference tip position of a reference tip of a reference probe on a probe card by a measuring instrument; displacing the inhomogeneous receiver in an aligning displacement according to the reference-pad-and-anisotropic-emitter relative position, the reference tip position and the receiver center position; and aligning the reference tip with the reference pad by a probe-tip-and-pad aligning machine of the wafer probing system.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: May 19, 2020
    Assignee: Win Semiconductors Corp.
    Inventor: Shu-Jeng Yeh
  • Patent number: 10643993
    Abstract: A compound semiconductor monolithically integrated circuit device with transistors and diodes comprises a compound semiconductor substrate, a transistor epitaxial structure, a transistor upper structure, a first diode, and a second diode. The transistor epitaxial structure forms on the compound semiconductor substrate. The first diode, the second diode, and the transistor upper structure form on a first part, a second part, and a third part of the transistor epitaxial structure, respectively. The transistor upper structure and the third part of the transistor epitaxial structure form a transistor. The first diode comprises a first part of an n-type doped epitaxial layer, a first part of a first intrinsic epitaxial layer, a first electrode, and a second electrode. The second diode comprises a second part of the n-type doped epitaxial layer, a second part of the first intrinsic epitaxial layer, a first electrode, and a second electrode.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: May 5, 2020
    Assignee: Win Semiconductors Corp.
    Inventors: Hsi-Tsung Lin, Yan-Cheng Lin, Sheng-Hsien Liu
  • Patent number: 10608608
    Abstract: A method for fabricating bulk acoustic wave resonator with mass adjustment structure, comprising following steps of: forming a sacrificial structure mesa on a substrate; etching the sacrificial structure mesa such that any two adjacent parts have different heights, a top surface of a highest part of the sacrificial structure mesa is coincident with a mesa top extending plane; forming an insulating layer on the sacrificial structure mesa and the substrate; polishing the insulating layer to form a polished surface; forming a bulk acoustic wave resonance structure including a top electrode, a piezoelectric layer and a bottom electrode on the polished surface; etching the sacrificial structure mesa to form a cavity; the insulating layer between the polished surface and the mesa top extending plane forms a frequency tuning structure, the insulating layer between the mesa top extending plane and the cavity forms a mass adjustment structure.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: March 31, 2020
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Chia-Ta Chang, Chun-Ju Wei, Kuo-Lung Weng
  • Patent number: 10594286
    Abstract: A method for forming cavity of bulk acoustic wave resonator comprising following steps of: forming a sacrificial epitaxial structure mesa on a compound semiconductor substrate; forming an insulating layer on the sacrificial epitaxial structure mesa and the compound semiconductor substrate; polishing the insulating layer by a chemical-mechanical planarization process to form a polished surface; forming a bulk acoustic wave resonance structure on the polished surface, which comprises following steps of: forming a bottom electrode layer on the polished surface; forming a piezoelectric layer on the bottom electrode layer; and forming a top electrode layer on the piezoelectric layer, wherein the bulk acoustic wave resonance structure is located above the sacrificial epitaxial structure mesa; and etching the sacrificial epitaxial structure mesa to form a cavity, wherein the cavity is located under the bulk acoustic wave resonance structure.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: March 17, 2020
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Chia-Ta Chang, Chun-Ju Wei, Kuo-Lung Weng
  • Patent number: 10580768
    Abstract: A GaAs (Gallium Arsenide) cell is provided. The GaAs cell comprises at least a GaAs substrates; a plurality of drain electrodes and a plurality of source electrodes, disposed on the at least a GaAs substrates; a gate electrode, disposed between the plurality of drain electrodes and the plurality of source electrodes, elongated along a first direction; a first anchor at a first end of the gate electrode; and a second anchor at a second end of the gate electrode; wherein a gate length of the gate electrode on a second direction is smaller than both a first width of the first anchor and a second width of the second anchor along the second direction.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: March 3, 2020
    Assignee: WIN Semiconductors Corp.
    Inventors: Jui-Chieh Chiu, Chih-Wen Huang, Shao-Cheng Hsiao
  • Patent number: 10553709
    Abstract: A heterojunction bipolar transistor, comprising an elongated base mesa, an elongated base electrode, two elongated emitters, an elongated collector, and two elongated collector electrodes. The elongated base electrode is formed on the base mesa along the long axis of the base mesa, and the base electrode has a base via hole at or near the center of the base electrode. The two elongated emitter are formed on the base mesa respectively at two opposite sides of the base electrode, and each of two emitters has an elongated emitter electrode formed on the emitter. The elongated collector is formed below the base mesa. The two elongated collector electrodes are formed on the collector respectively at two opposite sides of the base mesa.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: February 4, 2020
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Jui-Pin Chiu, Shu-Hsiao Tsai, Rong-Hao Syu, Cheng-Kuo Lin
  • Patent number: 10498310
    Abstract: A protective cover for an acoustic wave device and a fabrication method thereof, for protecting an acoustic wave device having a resonant area during a packaging operation so as to avoid molding compound flowing onto the resonant area of the acoustic wave device. The fabrication method comprises: defining a sacrificial area on the acoustic wave device; forming a sacrificial layer on the sacrificial area; covering a metal covering layer on the sacrificial layer and connecting a bottom rim of the metal covering layer to the acoustic wave device and forming an opening between the bottom rim of the metal covering layer and the acoustic wave device; and removing the sacrificial layer to form a cavity between the metal covering layer and the resonant area by using a chemical solution, wherein the chemical solution enters from the opening between the metal covering layer and the acoustic wave device.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: December 3, 2019
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Cheng-Kuo Lin, Shu-Hsiao Tsai, Rong-Hao Syu, Yi-Ling Liu, Re-Ching Lin, Pei-Chun Liao
  • Patent number: 10453805
    Abstract: A chip stack having a protection structure for semiconductor device package, which comprises a first chip and a second chip stacked with each other, wherein said first chip has a first surface, said second chip has a second surface, said first surface and said second surface are two surfaces facing to each other, wherein at least one metal pillar is formed on at least one of said first surface and said second surface and connected with the other, at least one protection ring is formed on at least one of said first surface and said second surface and having a first gap with the other, and at least one electrical device is formed on at least one of said first surface and said second surface, wherein said at least one electrical device is located inside at least one of said at least one protection ring.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: October 22, 2019
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Pei-Chun Liao, Po-Wei Ting, Chih-Feng Chiang, Yu-Kai Wu, Yu-Fan Chang, Re-Ching Lin, Shu-Hsiao Tsai, Cheng-Kuo Lin
  • Patent number: 10432200
    Abstract: A GaAs (Gallium Arsenide) cell is provided. The GaAs cell comprises a drain electrode and a source electrode, disposed on the GaAs substrate; a plurality of gate electrodes, disposed between the drain electrode and the source electrode, elongated on a first direction, wherein a gate electrode among the plurality of gate electrodes comprises a first end and a second end; a plurality of first anchors; a plurality of second anchors; wherein a first gate electrode and a second gate electrode among the plurality of gate electrodes are spaced by a gate-to-gate spacing, the first gate electrode and the drain electrode are spaced by a first gate-to-terminal spacing, and the gate-to-gate spacing is smaller than twice of the first gate-to-terminal spacing.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: October 1, 2019
    Assignee: WIN Semiconductors Corp.
    Inventors: Jui-Chieh Chiu, Chih-Wen Huang, Shao-Cheng Hsiao
  • Patent number: 10429413
    Abstract: A coaxial probe structure, comprising: a support member, comprising a first connecting member; a connector, comprising a second connecting member; a coaxial probe, connecting with a connecting end of the coaxial probe to a bottom of the connector, and extending downwards from the bottom of the connector to a probe tip, and an included angle formed at a junction of the probe tip and the connecting end; and an elastic body connecting the support member with the junction of the connecting end and the probe tip of the coaxial probe.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: October 1, 2019
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Shu-Jeng Yeh, Ju-Cheng Yu
  • Patent number: 10410979
    Abstract: An improved structure for reducing compound semiconductor wafer distortion comprises a contact metal layer and at least one stress balance layer. The contact metal layer is formed on a bottom surface of a compound semiconductor wafer; the at least one stress balance layer is formed on a bottom surface of the contact metal layer, wherein a thermal conductivity of the at least one stress balance layer is greater than or equal to 10 W/m-K. The stress suffered by the compound semiconductor wafer is balanced by the at least one stress balance layer, so that the distortion of the compound semiconductor wafer is reduced.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: September 10, 2019
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Chang-Hwang Hua, Wen Chu
  • Patent number: 10374129
    Abstract: An improved high temperature resistant backside metallization for compound semiconductors comprises a front-side metal layer formed on a compound semiconductor substrate; at least one via hole penetrating the compound semiconductor substrate, a top of an inner surface of the via hole is defined by the front-side metal layer; at least one seed metal layer, at least one backside metal layer and at least one diffusion barrier layer sequentially formed on a bottom surface of the compound semiconductor substrate and the inner surface of the via hole, the seed metal layer and the front-side metal layer are electrically connected through the via hole; a die attachment metal layer formed on a bottom surface of the diffusion barrier layer other than the via hole and an adjacent area near the via hole. The diffusion barrier layer prevents the backside metal layer from diffusing into the die attachment metal layer.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: August 6, 2019
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Chang-Hwang Hua, Shu Chen Chen, Huang-Wen Wang, Walter Tony Wohlmuth
  • Patent number: 10361272
    Abstract: An InGaAlP Schottky field effect transistor with AlGaAs carrier supply layer comprises a buffer layer, a channel layer, a carrier supply layer, a Schottky barrier layer and a cap layer sequentially formed on a compound semiconductor substrate; the cap layer has a gate recess, a bottom of the gate recess is defined by the Schottky barrier layer; a source electrode and a drain electrode are formed respectively on the cap layer at two sides with respect to the gate recess, the source electrode and the drain electrode form respectively an ohmic contact with the cap layer; a gate electrode is formed on the Schottky barrier layer within the gate recess, the gate electrode and the Schottky barrier layer form a Schottky contact; wherein the carrier supply layer is made of AlGaAs; the Schottky barrier layer is made of InGaAlP.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: July 23, 2019
    Assignee: Win Semiconductors Corp.
    Inventors: Shih-Ming Joseph Liu, Yu-Chi Wang, Cheng-Guan Yuan, Hsi-Tsung Lin, Chia Hsiung Lee
  • Patent number: 10298203
    Abstract: A chip stack having a protection structure for semiconductor device package comprises a first chip and a second chip stacked with each other. A first surface of the first chip and a second surface of the second chip are facing to each other. At least one metal pillar is formed on at least one of the first surface and the second surface and connected with the other. At least one protection ring is formed on at least one of the first surface and the second surface and having a first gap with the other. At least one electrical device is formed on at least one of the first surface and the second surface and is located inside at least one of the at least one protection ring, wherein the at least one electrical device includes a temperature sensor.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: May 21, 2019
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Pei-Chun Liao, Po-Wei Ting, Chih-Feng Chiang, Yu-Kai Wu, Yu-Fan Chang, Re-Ching Lin, Shu-Hsiao Tsai, Cheng-Kuo Lin
  • Patent number: 10256187
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate; a winding structure formed on a top side the semiconductor substrate, wherein the winding structure comprises one or more metal lines winding with respect to a center of the winding structure; and a backside metal formed under a backside of the semiconductor substrate; wherein a hollow slot is formed within the backside metal, and a projection of the winding structure is within the hollow slot.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: April 9, 2019
    Assignee: WIN Semiconductors Corp.
    Inventors: Jui-Chieh Chiu, Chih-Wen Huang, You-Cheng Lai