Abstract: A monolithic integration of enhancement mode (E-mode) and depletion mode (D-mode) field effect transistors (FETs) comprises a compound semiconductor substrate overlaid by an epitaxial structure overlaid by source and drain electrodes. The epitaxial structure includes from bottom to top sequentially a buffer layer, a channel layer, a Schottky barrier layer, a first etch stop layer, and a first cap layer. The respective first gate metal layers of the D-mode and E-mode FET are in contact with the first etch stop layer. The D-mode and E-mode gate-sinking regions are beneath the respective first gate metal layers of the D-mode and E-mode gate electrode at least within the first etch stop layer. The first gate metal layer material of the D-mode is the same as that of the E-mode, where the first gate metal layer thickness of the E-mode is greater than that of the D-mode.

Abstract: An InGaAlP Schottky field effect transistor with stepped bandgap ohmic contact, comprising: a buffer layer, a channel layer, a carrier supply layer, a Schottky barrier layer, an intermediate bandgap layer, a cap layer and an ohmic metal layer sequentially formed on a compound semiconductor substrate; wherein the Schottky barrier layer is made of InGaAlP; the ohmic metal layer and the cap layer form an ohmic contact. The Schottky barrier layer, the intermediate bandgap layer and the cap layer have a Schottky-barrier-layer bandgap, an intermediate bandgap and a cap-layer bandgap respectively, wherein the intermediate bandgap is less than the Schottky-barrier-layer bandgap and greater than the cap-layer bandgap.

Abstract: A stacked structure comprises a semiconductor chip which includes a substrate having at least one substrate via hole penetrating through the substrate; at least one backside metal layer formed on a backside of the substrate covering an inner surface of the substrate via hole and at least part of the backside of the substrate; at least one front-side metal layer formed on the front-side of the substrate and electrically connected to the at least one backside metal layer on a top of at least one of the at least one substrate via hole; at least one electronic device formed on the front-side of the substrate and electrically connected to the at least one front-side metal layer; and at least one metal bump formed on at least one of the backside metal layer and the front-side metal layer.

Abstract: An electroless plating apparatus and method designed specifically for plating at least one semiconductor wafer are disclosed. The apparatus comprises a container, a wafer holder, an electrolyte supplying unit, and an ultrasonic-vibration unit. The container is provided with at least an inlet and used for containing electrolyte. The wafer holder is provided within the container. The electrolyte supplying unit is used to supply the electrolyte into the container via the inlet. The ultrasonic-vibration unit consisting of at least one frequency ultrasonic transducer is disposed in the container for producing a uniform flow of electrolyte in the container. Thereby, the wafers can be uniformly plated, especially for wafers with fine via-holes or trench structures.

Abstract: An improved structure of the high electron mobility transistor (HEMT) and a fabrication method thereof are disclosed. The improved HEMT structure comprises a substrate, a channel layer, a spacing layer, a carrier supply layer, a Schottky layer, a first etch stop layer, a first n type doped layer formed by AlxGa1-xAs, and a second n type doped layer. The fabrication method comprises steps of: etching a gate, a drain, and a source recess by using a multiple selective etching process. Below the gate, the drain, and the source recess is the Schottky layer. A gate electrode is deposited in the gate recess to form Schottky contact. A drain electrode and a source electrode are deposited to form ohmic contacts in the drain recess and the source recess respectively, and on the second n type doped layer surrounding the drain recess and the source recess respectively.

Abstract: A method of processing copper backside metal layer for semiconductor chips is disclosed. The backside of a semiconductor wafer, with electronic devices already fabricated on the front side, is first coated with a thin metal seed layer by either electroless plating or sputtering. Then, the copper backside metal layer is coated on the metal seed layer. The metal seed layer not only increases the adhesion between the front side metal layer and the copper backside metal layer through backside via holes, but also prevents metal peeling from semiconductor's substrate after subsequent fabrication processes, which is helpful for increasing the reliability of device performances. Suitable materials for the metal seed layer includes Pd, Au, Ni, Ag, Co, Cr, Pt, or their alloys, such as NiP, NiB, AuSn, Pt—Rh and the likes. The use of Pd as seed layer is particularly useful for the copper backside metal layer, because the Pd layer also acts as a diffusion barrier to prevent Cu atoms entering the semiconductor wafer.