Abstract: A semiconductor device and a method for manufacturing the same are provided. The method includes forming a plurality of bit line structures on a semiconductor substrate, wherein there is a plurality of trenches between the bit line structures. The method also includes forming a first oxide layer conformally covering the bit line structures and the trenches, and forming a photoresist material layer in the trenches and on the first oxide layer, wherein the photoresist material layer has an etch selectivity that is higher than that of the first oxide layer. The method further includes removing the photoresist material layer to form a plurality of capacitor contact holes between the bit line structures, and forming a capacitor contact in the capacitor contact holes.

Abstract: A baffle device applied to a reaction room for isolating a specific matter is provided. The baffle device includes a main body, a first collecting assemble disposed around the main body and having plural first outlets and plural first collecting strips disposed on the plural first outlets for collecting the specific matter, and a second collecting assembly parallel to the first collecting assembly and having plural second outlets and plural second collecting strips disposed on the specific matter, wherein the first collecting strips and the second collecting strips are mutually arranged alternately.

Abstract: A method for transmitting a data to a rewritable nonvolatile memory through an interface port of a computer is proposed. The method comprising steps of: detecting the interface port; transmitting the data through the interface port of the computer; transmitting a part of the data; checking the part of the data for finding a miss condition; and transmitting the part of the data to the rewritable nonvolatile memory again according to the miss condition.

Abstract: An electrostatic discharge (ESD) protection device for protecting semiconductor devices against high-voltage transients due to electrostatic discharges. It includes: (1) an N-type well formed in a P-type semiconductor layer (or P-substrate); (2) a plurality of first P+ regions formed in the P-type semiconductor layer, wherein each of the first P+ regions is connected to an input,pad and is formed inside the N-type well; (3) a plurality of second P+ regions formed in the P-type semiconductor layer, wherein each of the second P+ regions is connected to the ground, at least one of the second P+ regions is outside the N-type well, and at least one of the second P+ regions is either in the N-type well or adjacent to it; and (4) an N+ region formed outside of the N-type well.

Abstract: A method is provided for manufacturing a memory cell with a increased threshold voltage accuracy. The memory cell has a substrate including a plurality of first conducting lines in a first direction and a plurality of second conducting lines in a second direction. The method includes the steps of forming a photoresist layer over the first and the second conducting lines, forming a window on the photoresist layer to expose a portion of the second conducting lines, thinning the portion of the second conducting lines in the windows, and doping impurities into the substrate between two of the first conducting lines to form the memory cell.

Abstract: In a method and apparatus for converting digitized luminance-chrominance color space signals to digitized RGB color space signals, a first combining unit generates a plurality of predetermined linear combinations of the chrominance color space signals received by a multiplexed multiplication unit which includes no more than two look-up tables that contain digitized transformation values for performing matrix multiplications of the linear combinations of the chrominance color space signals. A second combining unit linearly combines the digitized transformation values outputted by the multiplexed multiplication unit and a predetermined binary combination of the luminance color space signal in a first predetermined manner to generate three RGB color combination signals. A third combining unit linearly combines the RGB color combination signals in a second predetermined manner to obtain the RGB color space signals.

Abstract: An apparatus is used to process an original digital image to obtain a uniformly scaled desired digital image, the original digital image having a number (N) of successive original image data while the desired digital image has a number (M) of successive desired image data. When (M) is greater than (N), linear interpolation of (n)th and (n+1)th ones of the original image data is performed to produce a residual interpolated image data inserted therebetween when division of (M-N) by (N-1) results in a remainder (S) and when (n) is a minimum number which meets a condition (n+1)*(S).gtoreq.(s)*(N), wherein (s) ranges from 1 to (S). When (M) is less than (N), an address generator controls a memory unit to output selected ones of the original image data. A succeeding original image data outputted by the memory unit is offset from an immediately preceding original image data outputted thereby by a number (V) or by a number (V+1), the number (V) being equal to a quotient that results from division of (N) by (M).

Abstract: A discrete cosine transform (DCT) apparatus, capable of generating one-dimensional and two-dimensional DCT and inverse DCT results, uses six-stage DCT/IDCT fast algorithms to process a sequence of input data of an 8.times.8 data block. Each of the different stages of the DCT/IDCT fast algorithms involves a number of butterfly operations, which can be performed by a butterfly operation unit of the DCT apparatus, or a number of intrinsic multiplications, a number of post-addition multiplication operations, or a number of post-multiplication subtraction operations, all of which can be performed by a multiplication operation unit. A control unit of the DCT apparatus permits the use of a single butterfly operation unit and a single multiplication operation unit to perform the different stages of the DCT/IDCT fast algorithms. The results of each stage of the DCT/IDCT fast algorithms are stored in a data register unit of the DCT apparatus to serve as inputs for the succeeding stages of the DCT/IDCT fast algorithms.

Abstract: An image smoothing apparatus includes an image data providing device, an input buffer, a memory control unit, a horizontal mean value computing device, an intermediate stage memory device, a transverse mean value computing device, and an output buffer. The input buffer receives two original pixel data at each time from the image data providing device. One of the original pixel data is an nth pixel data of a ith column scan line, while the other one of the original pixel data is an nth pixel data of a (i+1)th column scan line. The horizontal mean value computing device receives the original pixel data from the image data providing device via the input buffer, and generates a smoothed image signal after all of the original pixel data have been processed. The smoothed image signal from the horizontal mean value computing device is stored in the intermediate stage memory device.

Abstract: A method for controlling a liquid crystal display (LCD) module to show interlaced picture data thereon includes the step of providing a data field of the interlaced picture data, which data field includes a series of line picture data, to the LCD module. Twin line clock pulses are then provided to the LCD module to control latching of each line picture data thereby. Finally, a frame start pulse is provided to the LCD module whenever a first one of the line picture data is provided to the LCD module. The width of the frame start pulse is varied so that the LCD module can show the first one of the line picture data on a first even line thereof when the data field is an even data field and on a first odd line thereof when the data field is an odd data field. The twin line clock pulses and the frame start pulse ensure that the line picture data of the even and odd data fields are shown alternately and respectively on even and odd lines of the LCD module.

Abstract: A telephone dialing device includes a data memory unit with a first memory region for storing normal dial numbers and a second memory region containing pre-stored memory dial numbers. A keypad is operated so as to provide a sequence of key inputs. The key inputs are decoded sequentially to determine if a normal or memory dialing activity is to be accomplished. A normal dial number corresponding to the decoded input is stored in the first memory region of the data memory unit, and a first code, which includes a normal dialing command and a first address to indicate the location of the normal dial number corresponding to the decoded input in the first memory region, is generated if the decoded input involves a normal dialing activity. A second code, which includes a memory dialing command and a second address to indicate the location of the memory dial number corresponding to the decoded input in the second memory region, is generated if the decoded input involves a memory dialing activity.

Abstract: In a method and apparatus for setting an address range for a computer expansion card of a computer system, the computer system is first controlled so as to execute a write operation which involves a series of addresses within the address range to be assigned to the computer expansion card. A linear feedback shift register receives the series of addresses from address lines of the computer system and derives a code output from the series of addresses. A code detecting unit receives the code output of the linear feedback shift register and compares the code output with a predetermined code. The code detecting unit generates a match signal whenever the code output matches with the predetermined code. An address register is activated by the match signal so as to store most significant bits of the address range to be assigned to the computer expansion card therein. The most significant bits are common to all of the addresses within the address range.

Abstract: A method for fabricating simultaneously bipolar and complementary MOS transistors is disclosed. After a gate oxide layer for the MOS transistors is grown, the gate oxide layer is etched to expose an intrinsic base region on a bipolar transistor well and to reduce thicknesses of opposite portions of base oxide layers that face one another on two sides of the intransic base region. Impurity is implanted into the intrinsic base region so as to form an intrinsic base of the bipolar transistor, the intrinsic base having a base portion between the base oxide layers and a base link portion connected to the base portion and disposed underneath the opposite portions of the base oxide layers. A polysilicon layer is then deposited on the gate oxide layer, and an impurity is implanted into the polysilicon layer and is driven through the polysilicon layer by high temperature treatment to form an emitter region on the surface of the base portion of the intransic base.

Abstract: A push-button telephone dialing device for a telephone set has a push-button keypad with a plurality of keys which include a hold function key, and a telephone dialing integrated circuit including a key input signal generator wired to the push-button keypad and producing an appropriate key input signal corresponding to a key pressed on the push-button keypad. The key input signal generator produces a hold function key input signal whenever the hold function key is pressed. The telephone dialing integrated circuit further includes a speech network interrupt circuit which receives the hold function key input signal from the key input signal generator. The speech network interrupt circuit is wired to and controls the operation of a speech network of the telephone set.