Abstract: A method of manufacturing a non-volatile semiconductor memory. The method includes forming a word gate poly layer on a substrate, wherein an upper surface of the substrate defines a plane of the substrate. The method also includes forming a first dielectric layer coupled to the word gate poly layer and patterning the word gate poly layer and the first dielectric layer to form an array of word gate structures. The method further includes forming a poly plug layer and patterning the poly plug layer to form a plurality of poly plugs surrounded in the plane of the substrate on three sides, forming a plurality of control gates, forming a second dielectric layer, planarizing the second dielectric layer using a chemical-mechanical polishing process, and depositing a metal layer to provide electrical contact to the word gate structures.

Abstract: Data input and output circuits that support multi data rate and a number of timing schemes. In one design, a data output circuit includes an input multiplexer, data latches, an output multiplexer, and at least one output driver. The input multiplexer receives a set of data bits in a first order (e.g., odd and even) and provides the data bits in a second order (e.g., first and second). The data latches can latch the data bits with (1) a latch signal to satisfy memory access timing requirements and (2) a data write clock signal to satisfy output timing requirements. The output multiplexer multiplexes the latched data bits to provide time multiplexed data bits. The output driver(s) provide signal drive for the time multiplexed data bits. Clock signals with various timing characteristics can be used to allow the data output circuit to satisfy various timing requirements.

Abstract: The present invention provides improved techniques for controlling current flow in an amplifier circuit. Specific embodiments provide steering of analog outputs of digital to analog converters in order to drive columns of an LCD display. Embodiments can provide a full range of voltage output to drive an LCD display without necessitating a full range amplifier configuration. Further, many specific embodiments can be realized in smaller space on an IC chip than in conventional technologies.

Abstract: A semiconductor memory column decoder has first and second groups of parallel column lines (or column line pairs). The first and second groups of column lines are separated from each other by a gap. One or more groups of fractional I/O lines are provided, wherein each fractional I/O line is collinear with each other fractional I/O line of the same group. One fractional I/O line is provided for, and is connected to, each column line of the first and second groups of column lines. A plurality of multiplexers is provided, including one multiplexer corresponding to each fractional I/O line. Each multiplexer has an input connected to a single data line, a select input connected to a corresponding column select line, and an output connected to the corresponding fractional I/O line. At least some of the multiplexers are disposed in the gap.

Abstract: A memory circuit column decoder is provided with an array of fuses that can be selectively blown to indicate a fuse address of a defective column of a memory array to be substituted by a redundant column. The memory circuit column decoder also includes a decoder that receives a mask that selectively masks out certain columns of a group of columns from being written during a block write operation, and the fuse address from the array of fuses. The decoder generates a signal for disabling the redundant column during a block write operation when the mask masks out the defective column.

Abstract: A precharge circuit is operable during a standby mode to drive a word line to a low voltage level and one or more (pairs of) bit lines to a standby voltage level. The precharge circuit comprises a driver for driving the on or more bit lines to the stand by voltage level. The precharge circuit also includes a control circuit connected to a control input of the driver which control circuit receives the standby signal. The control circuit outputs a varying enable signal to the driver for varying the drive of the bit lines by the driver. The precharge circuit can include a first current limiting driver for driving the bit lines to the standby voltage level, and second driver, for driving the bit lines to the standby voltage level. The second driver has a greater switching speed, and a higher current driving capacity, than the first current limiting driver.

Abstract: A method for presenting video on a local monitor and a remote monitor includes encoding an original video signal to produce a first compressed video signal. Using the first compressed video signal, the video signal is also encoded to produce a second compressed video signal. Both the first and second compressed video signals are transmitted to a local terminal at which the first and second compressed video signals are decoded to produce first and second decoded video signals. A first decoded version of the video signal is produced from a combination of the first and second decoded video signals. Only the first compressed video signal is transmitted to a remote terminal at which a second decoded version of the video signal is recovered from only the first compressed video signal.The first compressed video signal may be produced by motion compensation temporally encoding and spatially encoding the original video signal.