Abstract: The invention provides a memory device having page select capability. The serial access memory device provided includes a first data terminal and a memory cell array having a plurality of address locations. The serial access memory device including a shift register, an address decode circuit and a page select device. The page select device, in response to the access control signal, the address clock signal and the clock signal, selectively stores a page number therein.

Abstract: An automatic code pattern generator apparatus is disclosed which has a processor. The processor is for receiving a plurality of instructions including an instruction indicating a particular polygon specification associated with cells of at least one physical layer of a pre-programmed integrated circuit chip. The processor also receives at least one instruction indicating a regular ordered pattern of a plurality of the cells on the physical layers of the pre-programmed integrated circuit chip. The processor generates a code layer including a design of a layout of the polygons according to the regularly ordered pattern on the physical layers of the pre-programmed integrated circuit. The generated code layer also includes a mapping relationship between cell addresses, and corresponding ones of the cells associated with the polygons. The processor may also receive information indicating variations in particular addressed cells associated with the polygons of the regularly ordered pattern of cells.

Abstract: An apparatus adapted to be activated by an input device for accessing a function code in a telephone comprises a first memory for storing a function code, a second memory electrically connected to the first memory for storing a datum corresponding to the function code, and an address decoder electrically connected to the input device and the second memory for decoding a signal generated from the input device and designating thereby an address to access at least one of the function code and the datum, wherein the function code stored in the first memory and the datum stored in the second memory are accessible by same the address. This apparatus effectively reduces the number of the keys required on a keypad of a telephone and is provided for a simplified operation.

Abstract: A device for detecting an operation state of a telephone hook switch in a telephone includes a timer, a controlling circuit, a counter and a table electrically interconnected. According to the present invention, the abnormal signals generated by the hook switch cannot be accepted by an exchange or even if the signals are accepted by the exchanger, the mute function of the telephone will be utilized to make the users unable to listen to each other.

Abstract: A method and apparatus for prohibiting unauthorized use of a telecommunication line is provided. An interference signal is timely generated by the invention on the telecommunication line such that the illegitimate user may not dial the number correctly. Therefore, the invention may prohibit the unauthorized use of a telecommunication line.

Abstract: In accordance with the invention, the emitter region of a BJT is formed prior to the formation of the base contact regions so that the base contact regions are not enlarged during a thermal cycle used to form the emitter and the base contact regions remain small. Preferably, the base contact regions are formed by ion implantation after the emitter is formed. In addition, the base interconnect links may be metal (or polycide) rather than polysilicon so that the base interconnect resistance is reduced.This results in the following advantages:(1) reduced emitter-base junction leakage(2) reduced collector-base junction capacitance.(3) reduced base interconnection series resistance.

Abstract: The present invention provides a circuit for use in an ADPCM synthesizer for generating a function of a quantization step without the use of a look-up table. Illustratively, the function is represented in a piecewise linear fashion. This permits an ADPCM synthesizer to be implemented without the use of a memory storing a look-up table for the function so the area of the synthesizer chip can be reduced.

Abstract: The present invention is related to an isolation method for SOI (Silicon on Insulator) devices on an SOI wafer having a silicon substrate, a buried dielectric layer formed on the silicon substrate and a silicon film layer formed on the buried dielectric layer.

Abstract: An ESD protection device is disclosed having a first region of a first conductivity type. A second region, which is heavily doped, of a second conductivity type is disposed in the first region. The second region extends from the surface of the first region a first depth. A third region, which is heavily doped, of the second conductivity type, is also disposed in the first region such that the third region is separated from the second region by a portion of the surface of the first region. The third region extends from the surface of the first region a second depth less than the first depth of the second region. An insulating region is grown on a portion of the surface of the first region between the second and third regions. Furthermore, a resistive conducting region is disposed on the second region and the insulating region. A portion of the resistive conducting region extends beyond the second region for receiving an input signal.

Abstract: In accordance with the invention, the emitter region of a BJT is formed prior to the formation of the base contact regions so that the base contact regions are not enlarged during a thermal cycle used to form the emitter and the base contact regions remain small. Preferably, the base contact regions are formed by ion implantation after the emitter is formed. In addition, the base interconnect links may be metal (or polycide) rather than polysilicon so that the base interconnect resistance is reduced. This results in the following advantages: reduced emitter-base junction leakage, reduced collector-base junction capacitance, and reduced base interconnection series resistance.

Abstract: The invention inputs a single timing clock. Through procedure of mode setting, the invention generates the required timings corresponding to the display mode selected. In the invention, a programmable mode register, a mode decoder, a pixel timing generator, a horizontal timing generator, a vertical timing generator, a composite timing generator, AND gate, EXCLUSIVE NOR gate, and a selector are provided. The invention may generate the required timings for NTSC interlace mode, NTSC non-interlace mode, PAL interlace mode, PAL non-interlace mode, VGA 60 Hz progressive mode and VGA 50 Hz progressive mode.

Abstract: A process for manufacturing a MOSFET having a shallow junction of a doped region includes preparing an intermediate wafer product, applying an oxide layer on said intermediate wafer product, introducing into a dopant around an interface between said oxide layer and said intermediate wafer product, and driving said dopant into said intermediate wafer product to form a MOSFET having a relatively shallow junction of a doped region. This invention offers a simplified, efficient, and cost-effective process to obtain a MOSFET having a relatively shallow junction of a doped region and being free from electrical leakage possibly occurred at the junction.

Abstract: A self aligned lateral BJT is disclosed which has a lightly doped first region of a first conductivity type, e.g., P-type. A heavily doped polysilicon region, of a second conductivity type, e.g., N-type, is provided on a portion of a surface of the first region. A heavily doped second region of the second conductivity type, is disposed in the first region below the polysilicon region. An oxide region is provided on a portion of the first region surface adjacent to the polysilicon region. A third region of the first conductivity type is disposed in the first region adjacent to the second region and below the oxide region. A heavily doped fourth region of the second conductivity type is disposed in the first region adjacent to the third region. The fabrication of the lateral BJT includes the step of forming a polysilicon region on a portion of the first region. Then, the second region is formed by diffusing an impurity from the polysilicon region into the first region.

Abstract: A self-aligned contact process for making an MOS device results in an MOS device with a small and repeatable interconnect size, repeatable interconnect resistance, and reduced source/drain junction capacitance.

Abstract: A high frequency clock generator has a plurality of quartz crystals capable of providing various output frequencies coupled to multiple oscillator circuits. The output line from each oscillator circuit is coupled to one or more multiplexers so that the user can select one or more output frequencies at the same time. The multiple clock oscillator circuits and the multiplexer(s) are fabricated as an integrated circuit to minimize the degrading effects of weather and dust, to provide a fixed capacitive value and inverter bandwidth product, and to improve clock generator stability.

Abstract: A small and shrinkable EEPROM cell and method of forming such a cell are provided which includes a control gate having a reentrant profile and a side-wall floating gate conforming to that profile. A predetermined portion of the floating gate overlies the source region which accelerates programming speed. The reentrant profile of the floating gate under the control gate accelerates erasing of the cell. Because of the self-aligned structure of the cell, the EEPROM has a small cell area and is insensitive to layer misalignment. Because of its configuration, the EEPROM cell is easily incorporated into an array of like cells sharing a common source region which facilitates "flash" erasing.