Abstract: A monotonic counter includes a plurality of stages respectively corresponding to a plurality of counting bits of the monotonic counter. At least one of the plurality of stages is a non-volatile flip-flop (NVFF) counter that includes a plurality of NVFFs, each NVFF including a pair of non-volatile memory cells.

Abstract: A flash memory device may operate from two supply voltages, one being provided externally, and the other being generated within the flash memory device from the external supply voltage. The flash memory device may be provided with a selectable-level buffer for interfacing with either low supply voltage or high supply voltage integrated circuits. To provide even greater flexibility, the flash memory device may be provided with the capability of receiving a second supply voltage from an external source, which may take precedence over the internally-generated second supply voltage or may be combined with the internally-generated second supply voltage.

Abstract: Capacitive detection systems, modules, and methods. In one embodiment, time interval measurement(s) are generated that are monotonic functions of the capacitance(s) of capacitive sensor(s) in a capacitive sensing area. In one embodiment, the generated time interval measurement(s), or any other monotonic function(s) of capacitance(s) of capacitive sensor(s) in a capacitive sensing area, may be analyzed to detect the presence of an object near the capacitive sensing area and/or to detect the position of an object near the capacitive sensing area.

Abstract: The present invention discloses a frequency signal enabling apparatus and the method thereof for filtering noises and glitch when entering an operating mode from a power-saving mode. When the pulse width of the input frequency signal is smaller than the threshold pulse width, it will be considered as a noise and be filtered out. When the high-level pulse width of the input frequency signal is greater than the threshold, a first short pulse will be generated. When the low-level pulse width of the input frequency signal is greater than the threshold, a second short pulse will be generated. The relative position of the first short pulse and the second short pulse will be used to reconstruct the frequency signal, and the reconstructed frequency signal may serve as the operating frequency of the microprocessor or other digital IC.

Abstract: A multilevel analog recording and playback system is described. An analog processing circuit processes analog data. A storage circuit includes a non-volatile memory array, a switching circuit, and a communication interface. The non-volatile memory array stores analog and digital data. The switching circuit transfers the analog and digital data to and from the memory array. The communication interface allows a processor to exchange information with the device.

Abstract: A memory device with high charging voltage bit lines, comprising: memory cells, sense amplifiers, and high charging voltage bit line circuits. Herein, the memory cell is used to store data and electrically couples with a pair of bit lines. The sense amplifier with a pair of sense nods, which electrically couples with the pair of bit lines, is used to sense the differential voltage levels of the pair of sense nodes while the memory cell is active. The high charging voltage bit line circuit is used to provide a charging voltage, which is higher than the logical high voltage of the memory cell, for charging the memory cell.

Abstract: A method and system of monitoring apparatuses of manufacturing integrated circuit (IC) detects the problems during wafers processing by replaying the apparatus events. First, the method and system download the data of apparatus events, and then calculate the achievement indices. Then, the method and system establish the control chart to determined limitative rules, and execute the replaying system by establishing the computer interface system therewith to detect the abnormal point so as to proceed a rectification. The method and system of monitoring apparatuses of manufacturing IC review the past achievements by establishing a model for replaying apparatus history and achievements, and foresee the future problems by establishing control charts and a knowledge archive of rules.

Abstract: A method of forming a semiconductor memory having rows and columns of memory cells is as follows; forming a plurality of rows of program gate lines from a second layer polysilicon; forming a plurality of rows of select gate lines from a third polysilicon layer; forming a plurality of rows of diffusion source lines: forming a plurality of local bitlines from a first layer metal, the cells along each column being divided into a pre-designated number of groups, and drains of the cells in each group being connected to a local bitline extending across the cells in the group of cells; and forming a plurality of global bitlines from a second layer metal extending along every two columns of cells, each global bitline being configured to selectively provide electrical connection to the local bitlines along the corresponding two columns of cells.

Abstract: A balanced current converter with multiple PWM converter channels has an error amplifier, a main converter channel and at least one parallel converter channel. The converter provides a DC power output and feeds back an average output voltage signal. The error amplifier compares a reference voltage signal and the average output voltage signal to generate an error signal. The main converter channel outputs a main channel current signal and a main channel power output according to the error signal. The parallel converter channel compares the main channel current signal and the respective parallel channel current signal to generate a first deviation signal, then compares the first deviation signal and the error signal to generate a second deviation signal. The parallel converter channel provides and measures a respective parallel channel power output to feed back the respective parallel channel current signal.

Abstract: The present invention discloses a method for manufacturing a flash memory cell having a horizontal surrounding gate (HSG). The flash memory cell of the present invention is formed on a trench of an isolation region, and a channel of the flash memory cell composed of a semiconductor film is encompassed and surrounded by a tunneling oxide layer, a floating gate, a dielectric layer, and a control gate in sequence. In addition, the floating gate and the control gate are also formed on the trench below the channel. Therefore, the leakage current of the channel can be reduced, and the short channel effect can be avoided. Furthermore, the coupling capacitor between the control gate and the floating gate is increased without increasing the cell size. Besides, the data can be programmed and erased by a Fowler-Nordheim (FN) tunneling effect.

Abstract: A stable voltage converter is described. The converter has multiple pulse width modulated channels having an error amplifier and a plurality of converter channels. The error amplifier compares the reference voltage and the average output voltage to generate an error signal for stabilizing the output voltage of the converter. Each converter channel uses the error signal input and generates a direct current power output. Furthermore, each converter channel includes a subtraction circuit, a pulse width modulator, a power switch, a filter and a current sensor. The subtraction circuit coupled with the error amplifier inputs the error signal and a channel current signal proportional to the direct current power output; therefore, the subtraction circuit subtracts the channel current signal from the error signal and outputs a modified error signal. The pulse width modulator inputs the ramp signal and the modified error signal then outputs the pulse width modulator signal.

Abstract: The present invention discloses a standby current erasion circuit applied in DRAM, which improves prior art word line driving circuit to have the word line voltage outputted in standby mode be equal to the bit line voltage, thereby the short DC standby current between the word line and bit line can be erased.

Abstract: The present invention discloses a simple and convenient method for fabricating a capacitor device with BiCMOS processes. An electrode of the capacitor device formed according to the present invention is an ion doping region formed in an epitaxy layer so that the thickness of the dielectric layer of the capacitor device decreased relative to a specific ion concentration. Accordingly, the capacitor device formed therein has a high capacitance and good performance.

Abstract: The present invention discloses a structure of a flash memory cell having a horizontal surrounding gate (HSG) and a method for manufacturing the same. The flash memory cell of the present invention is formed on a trench of an isolation region, and a channel of the flash memory cell composed of a semiconductor film is encompassed and surrounded by a tunneling oxide layer, a floating gate, a dielectric layer, and a control gate in sequence. In addition, the floating gate and the control gate are also formed on the trench below the channel. Therefore, the leakage current of the channel can be reduced, and the short channel effect can be avoided. Furthermore, the coupling capacitor between the control gate and the floating gate is increased without increasing the cell size. Besides, the data can be programmed and erased by a Fowler-Nordheim (FN) tunneling effect.

Abstract: The present invention provides a regulator used in an active terminator of a bus. The regulator comprises a voltage-regulated terminal, a first operational amplifier and a non-inverting input terminal thereof coupled to a reference voltage. An inverting input terminal of a second operational amplifier is coupled to the reference voltage. A control gate of a first transistor is coupled to an output terminal of the first operational amplifier. A source of the first transistor is coupled to an inverting input terminal of the first operational amplifier to form a feedback network and to provide a stable circuit of sourcing current. A control gate of a second transistor is coupled to an output terminal of the second operational amplifier and a drain of the second transistor to a non-inverting input terminal of the second operational amplifier to form the feedback network and to provide a stable circuit of sinking current.

Abstract: The present invention discloses a current comparator having simple, cheap and fast characteristics, especially discloses a current comparator having a small dead zone and excellent driving capability. The current comparator of the present invention comprises a first CMOS transistor, a second CMOS transistor, a diode-configured N-type transistor, a fourth CMOS transistor and a fifth CMOS transistor.

Abstract: A method for forming shallow trench isolations includes the steps of defining a wafer substrate, forming a silicon dioxide insulating layer on the substrate, depositing a silicon nitride layer on the silicon dioxide insulating layer, and forming at least one trench in the substrate through the silicon dioxide and silicon nitride layers. The method also includes the steps of depositing a silicon dioxide layer over the silicon nitride layer and in the trench, removing the silicon dioxide layer deposited over the silicon nitride layer, anisotropically etching the silicon dioxide layer to produce silicon dioxide sidewalls in the trench contiguous with the silicon nitride layer, isotropically etching to remove the sidewalls and removing the silicon nitride layer.

Abstract: An analog memory device includes a memory cell transistor and a memory follower transistor that share a common floating gate. The drain of the memory cell transistor is coupled to a first voltage source. The control gate of the memory cell transistor is coupled to a second voltage source. A programming transistor is coupled between the source of the memory cell transistor and a reference voltage. A comparator receives a first input analog signal to be stored in the memory cell transistor and is coupled to the memory follower transistor to receive the signal held on the floating gate. The output of the comparator is coupled to the control gate of the programming transistor to selectively turn it on to store the analog signal in the memory cell transistor.