Abstract: A NAND flash memory achieves low read latency and avoidance of inadvertent programming and program disturb so that the random access and initial page read speeds of the NAND flash memory are generally comparable to that of a NOR flash memory, while preserving the higher memory density and lower power operation characteristics of traditional NAND flash memory relative to NOR flash memory. The reduction in latency is achieved by a NAND memory array architecture which employs a small NAND string, a dual plane interleaved memory architecture, a partitioned NAND array, selectively coupled local bit lines per each global bit line, and a counter-biasing mechanism to avoid inadvertent programming and program disturb.

Abstract: A current sorter has an input section, a comparing section, and a control section. The input section includes a first input unit and a second input unit and generate a first output signal that is indicative of the first input signal and a second output signal that is indicative of a level of the second input signal. The comparing section is coupled with the input section and compares the first output signal and the second output signal to responsively generate a result. The comparing section includes a first comparing unit and a second comparing unit. The control section is coupled with the input section and the comparing section. Furthermore, the control section activates, when receiving an initial load signal, the first input unit, the second input unit, the first comparing unit, and the second comparing unit.