Abstract: A computer imaging communications system includes a camera head having a CCD for the capture of video images according to a set of timing signals. The timing generator for the CCD is state-based such that state transitions in the CCD control logic can be controlled by a host computer or a camera adapter circuit. The set of timing signals provided to the CCD are generated in the camera head in response to a control/data signal generated by a controller which combines a clock with a coded control signal. The clocking signal has a variable frequency to allow video data to be generated at an arbitrary rate. First and second video signals defining a unique color space are output from the camera head and transmitted across a cable to the adapter card or host computer, where it is received for further processing.

Abstract: A computer architecture that can rapidly perform a variety of repetitive mathematical operations on multimedia data sets comprises a data processing engine having n data processing devices, each of which includes shift registers and multiplexers for organizing input data into bit slices such that each of the n data processing devices can receive one bit of information from n data samples. Look-up operations are performed in a table memory of each of the n data processing devices on a bit slice, the table memory containing all possible combinations of a constant function. The results of the look-ups are shifted and accumulated to simultaneously generate multiple outputs of a convolution of an input function with the constant function. A data path provides information transfer between each of the n data processing devices.