Abstract: A harmonic filter for filtering a plurality of frequency components from an input signal comprises a phase shifter for generating an in-phase signal and a quadrature-phase signal according to the input signal; and a plurality of polyphase filter networks coupled in series. The first polyphase filter network in the series is coupled to the phase shifter for receiving the in-phase and quadrature-phase signals. Each polyphase filter network is for filtering a corresponding one of the frequency components from the input signal.

Abstract: Certified Wireless USB 1.0 defines two different types of association: cable association and numeric association. In order to implementation these two association methods, the CWUSB device needs to have either upstream USB connector (for cable association) or display capability (for numeric association). These extra requirements make the CWUSB device bulkier (one more USB connector) and/or more expensive (extra display components). For cheap and simple CWUSB devices, we need a simpler association method that is easy and cheap to implement. In a pre-packaged total solution, which includes a host and one or more device(s), we can use pre-association to smooth the user experience. The host and device(s) are pre-associated. When an end user starts to use this solution, they do not need to worry about the association at all.

Abstract: Universal Serial Bus (USB) is a Master/Salve or Host/Device system in which there is only one host and one or more devices connected by cables to the host. To connect a USB device to a different host controller (say another PC), the user unplugs the USB cable and establishes the connection physically by plugging the cable into the new host controller interface. Certified Wireless USB (CWUSB), a logical extension to the USB, preserves the USB connection model, except that the link between the host and the device is now using a wireless technology. A wireless device is usually connected to only one wireless host at a given point of time, even though several wireless hosts may be co-located in the same physical neighborhood. The connection between the wireless host and device is initiated by the device. A device usually selects a wireless host from a stored set of known hosts that have established a trusted relationship with the device.

Abstract: Certified Wireless USB 1.0 (CWUSB) defines two different types of association: cable association and numeric association. In the numeric association, the CWUSB host and device use a specific protocol to exchange the security information. At final stage of this information exchange, both host and device need to display a number asking user's feedback. Once this is done, both host and device will be able to generate the connection key as the shared secret for the following secured communication. One problem of this numeric association method is that device needs to be able to display the numbers. For certain class of device that has capability to display an image, there is a natural way to add this function to them. A method for this class of devices is described. Another kind of association, which is not defined in the CWUSB 1.0, is manual association. User needs only to manually type in the Connection Key coming from the CWUSB device.

Abstract: The inventive technique can dynamically adjust the current being applied within the components of a prescaler or divider. This dynamic scaling of the current can improve the speed of the divider by a factor of two or reduce the average current in half when compared to the conventional prescaler. Inverters are used to directly adjust the dynamic value of the currents. The removal of the conventional NMOS device within the conventional circuit eliminates one gate delay in the CML prescaler. Second, the inventive prescaler circuits operate under a current injection/extraction technique. A group of small matched inverters can be used to drive each current switching circuit independently within the entire prescaler as compared to a large buffer driving the entire conventional prescaler. Finally, dynamic current scaling offers the designer additional flexibility in the design trade off between the maximum current applied to the load and achieving the maximum performance.

Abstract: The inventive technique can dynamically adjust the current being applied within the components of a prescaler or divider. This dynamic scaling of the current can improve the speed of the divider by a factor of two or reduce the average current in half when compared to the conventional prescaler. Inverters are used to directly adjust the dynamic value of the currents. The removal of the conventional NMOS device within the conventional circuit eliminates one gate delay in the CML prescaler. Second, the inventive prescaler circuits operate under a current injection/extraction technique. A group of small matched inverters can be used to drive each current switching circuit independently within the entire prescaler as compared to a large buffer driving the entire conventional prescaler. Finally, dynamic current scaling offers the designer additional flexibility in the design trade off between the maximum current applied to the load and achieving the maximum performance.

Abstract: Multistage RF transmitter and receiver circuits may use independently variable RF and IF local oscillators, allowing the RF and IF local oscillator frequencies for a given RF channel to be selected to have a large common factor with respect to the reference oscillator used by the local oscillator circuits, thus allowing the use of small divisor numbers in the local oscillator circuits and reducing phase noise. Independent high-side and low-side RF local oscillators may be provided and selectively used depending on the RF channel to be transmitted or received.

Abstract: The present invention describes a transmitter/receiver architecture that uses a Weaver architecture in conjunction with digitally controlled adder/subtractor components to insert/extract a signal into/from the multi-channel system. In the transmitter, the selection of the band select bit causes the up/downconverted IF baseband I and Q signals to insert/extract on either side of an RF LO signal. In addition, the image of the first LO is eliminated while the desired signal is enhanced after passing through this new architecture. The invention also adds an RSSI circuit to the MBOA Weaver architecture receiver architecture to detect whether an 802.11 WLAN signal is interfering with the desired UWB signal. If so, the system is designed to detect this interference and jump to a new frequency range to avoid this interference. This invention focuses on devices that operate over the entire UWB band including the newly formed 60 GHz UWB band system.

Abstract: The present invention provides reduces the number of required synthesizers thereby reducing the area and power concerns to extract/insert a signal from/to a multi-channel communication system and is also known as frequency planning. The highest frequency of operation required for the synthesizers or oscillators is approximately the midpoint of the entire signal frequency range. Two superimposed Weaver architectures are used to form the architecture. The receiver extracts the baseband I and Q signals from the multi-channel communication system, while the transmitter upconverts the baseband I and Q signals to the multi-channel communication system. The Weaver architecture, depending on the select bit, can enhance the image signal and reduce the desired signal or the image signal can be reduced while the desired signal is enhanced. Because the image and signal components are symmetrically displaced from the RF LO, less IF LO frequencies or synthesizers are required to operate the system.

Abstract: A signal is applied to the body of a MOSFET to enhance the transconductance of the MOSFET. The signal applied to the body of the MOSFET has essentially the same waveform as an input signal supplied to the gate of the MOSFET, and is shifted by approximately 180 degrees with respect to the input signal. The signal applied to the body of the MOSFET may be provided by a phase-adjusting feedback circuit that generates the signal from a signal representing the output of the MOSFET.

Abstract: Systems and methods for canceling static and dynamic DC offsets by combining a digital DC offset correction scheme with an analog DC offset correction scheme. A feedback-based digital DC offset correction scheme provides different adjustment levels for a plurality of discrete gain states and the analog DC offset correction scheme operates in different cancellation modes dependent on a frame structure. A digital DC offset correction scheme collects DC offset control information and provides adjustment levels. In addition, a negative-feedback based switchable high pass filter has a plurality modes of operation, where one mode of operation includes an all-pass filter.

Abstract: First, second, third, and fourth resistors are coupled to first, second, third, and fourth capacitors. A first positive in-phase terminal is coupled to the first resistor and the first capacitor. A first negative in-phase terminal is coupled to the fourth resistor and the fourth capacitor. A positive quadrature-phase terminal is coupled to the second resistor and the first capacitor. A second positive in-phase terminal is coupled to the first resistor and the second capacitor. A second negative in-phase terminal is coupled to the fourth resistor and the third capacitor. A negative quadrature-phase terminal is coupled to the third resistor and the fourth capacitor. The first and fourth resistors, the second and third resistors, the first and fourth capacitors, and the second and third capacitors are equal distances from and on a same side of respective axes, and are equal distances from and on opposite sides of a symmetry axis.

Abstract: Delays are produced in differential signals using a variable capacitance provided by MOS varactors coupled between the differential signals. The capacitance values of the MOS varactors is controlled by a bias voltage applied to the bodies of the varactors. Selective application of bias voltages to the MOS varactors may be employed to selectively delay one pair of differential signals with respect to another pair of differential signals so as to change the relative phases of the signals. A logic circuit may be used to control the application of bias voltage to the MOS varactors so that signal phases may be adjusted in a manner that is predictable and programmable. These methods may be implemented to compensate for phase offsets between in-phase and quadrature signals of a local oscillator.

Abstract: A feedback system has a settling time that is independent of the forward gain of the amplifier stage, and a feedback path that is responsive to the magnitude of DC offset in the output signal. Settling time may be made independent of the forward gain of the amplifier stage by providing a constant loop gain in the amplifier stage through active gain control of both the forward and linear feedback amplifier elements. The feedback path may be made responsive to the magnitude of DC offset in the output signal by providing a non-linear transconductance in the feedback path that varies the high pass corner and hence the DC offset reduction time of the amplifier stage in response the magnitude of DC offset in the output signal.

Abstract: A charge pump circuit utilizes active feedback control circuits to control the currents produced by sinking and sourcing current sources. The feedback control circuits may regulate the drain voltages of sinking and sourcing current source transistors to make them approximately equal to respective reference voltages received by the feedback control circuits. The charge pump circuit may utilize multiple supply voltages, with a higher supply voltage such as a 3.3 V supply voltage being used to drive current source transistors, and a lower supply voltage such as a 1.8 V supply voltage being used to drive switches in a switching section.

Abstract: An output stage circuit for a current mode device provides open loop reduction or cancellation of DC offset in differential output signals. Differential input signals are received and sourcing current mirrors provide mirrors of the differential input signals to output nodes. Sinking current mirrors also provide mirrors of opposite polarity of the differential input signals to the output nodes corresponding to the opposing sourcing current mirrors. The summing of the mirror currents at the output nodes substantially reduces or eliminates the DC offset components present in the input signals.