Abstract: A fractional-N frequency synthesizer is based on a PLL which employs a multi-phase VCO and a multi-phase frequency divider to provide a desired fractional-N divider ratio. The multi-phase frequency divider includes a multi-modulus divider which divides a VCO output waveform with a division ratio that varies in response to a modulus control signal. The divided output is delayed to produce a plurality of outputs, each of which has a respective phase that corresponds with the phase of a respective VCO output. A phase selector provides a selected one of the outputs to the PLL's phase detector in response to a phase control signal such that the multi-phase frequency divider provides a fractional-N division ratio. To reduce fractional spurs, a modulator randomizes the modulus and phase control signals, which serves to randomize and thereby reduce phase mismatch error which might otherwise be present in the frequency synthesizer's output.

Abstract: A bit slicer circuit and method detect the peak of the differential slope in a demodulated data signal received via a wireless data system, so that bit slicing can be insensitive to DC fluctuations. This is accomplished by detecting when the demodulated signal transitions by more than a predetermined threshold value Vth during each symbol period, and determining the polarity of a detected transition. A latch is set and a logic “1”, is output when the polarity of a detected transition is negative; the latch is reset and a logic “0” is output when the polarity is positive.