Patents Assigned to Wiscosin Alumni Research Foundation
  • Computer Cache System Providing Multi-Line Invalidation Messages
    Publication number: 20140101390
    Abstract: A computer cache system delays cache coherence invalidation messages related to cache lines of a common memory region to collect these messages into a combined message that can be transmitted more efficiently. This delay may be coordinated with a detection of whether the processor is executing a data-race free portion of the program so that the delay system may be used for a variety of types of programs which may have data-race and data-race free sections.
    Type: Application
    Filed: October 8, 2012
    Publication date: April 10, 2014
    Applicant: Wiscosin Alumni Research Foundation
    Inventors: Gurindar S. Sohi, Hongil Yoon