Abstract: Driving methods for display panels are provided, in which a Kth row of pixels in a pixel array is driven during a first period, and a K+1th row of pixels in the pixel array is driven during a second period. A control clock applied for a charge pump is toggled at least N times during a third period between the first and second periods, and the control clock is maintained at a fixed logic level during the first and second periods, in which N?2.

Abstract: An image sensor module having a light gathering region and a light non-gathering region includes an image sensor, a lens barrel and a lens layer. The lens barrel is disposed on the image sensor and located in the light non-gathering region and has a through hole exposing a portion of the image sensor in the light gathering region. A material of the lens barrel includes a thermoplastic with a melting point higher than soldering temperature. The lens layer is disposed on an end portion of the lens barrel away from the image sensor and covers the through hole. The lens layer includes a glass substrate and a lens disposed on the glass substrate and located in the light gathering region.

Abstract: A wafer level optical apparatus includes a wafer level lens unit for receiving light. The wafer level lens unit includes a lens substrate having a partial surface with a slope greater than zero and at least one lens adhered to a surface of the lens substrate.

Abstract: An optical zoom system including a photo sensor, a wafer level optical (WLO) lens module and a focusing motor is provided. The WLO lens module is located at the photo sensor. The WLO lens module includes at least one transparent substrate and at least one lens, wherein the lens is disposed on the transparent substrate. The focusing motor is located between the WLO lens module and the photo sensor. The focusing motor drives the WLO lens module to move toward or backward the photo sensor.

Abstract: A wafer level optical imaging apparatus includes a covering substrate that covers an imaging unit. A top shading layer is formed on a top surface of the covering substrate, and a bottom shading layer is formed on a bottom surface of the covering substrate.

Abstract: A fabricating method and structure form a wafer level module with a solid adhesive film. A first solid adhesive film includes a first release film and a second release film that respectively cover a first surface and a second surface of the first solid adhesive film. Openings are patterned through the first solid adhesive film. After removing parts of the first release film to expose the first surface of the first solid adhesive film, the exposed first surface of the first solid adhesive film is aligned and adhered to a first substrate.

Abstract: A gamma voltage generator generating a plurality of gamma voltages transformed into a plurality of data signals by a processing unit is disclosed. The processing unit outputs the data signals according to a color separation method. The gamma voltage generator comprises a setting unit, a resistor string, and a selection unit. The setting unit provides a first parameter, a second parameter, and a third parameter. The resistor string generates the gamma voltages according to the first, second, or third parameter. The selection unit is coupled between the setting unit and the resistor string for outputting the first, second, or third parameter to the resistor string according to a control signal group.

Abstract: An operating frequency generating method and circuit for a switching voltage converter are provided. The method includes the following steps. First, a reference clock signal and a digital period signal are received. The phase of the digital period signal is delayed according to at least one different delay time, so as to generate at least one delay period signal. The digital period signal or one of the delay period signals is selected as an operating frequency of the switching voltage converter at every predetermined time interval.

Abstract: A glitch suppressing apparatus is provided. The glitch suppressing apparatus comprises four N-type transistors, four P-type transistors, a first delay circuit, a second delay circuit, a first logic circuit, a second logic circuit and two inverters. The glitch suppressing apparatus uses the specific connection relations and functions of the above components to filter positive glitches and negative glitches in the same circuit, so that the glitch suppressing apparatus can be implemented on a smaller chip area.

Abstract: A glitch suppressing apparatus is provided. The glitch suppressing apparatus comprises four N-type transistors, four P-type transistors, a first delay circuit, a second delay circuit, a first logic circuit, a second logic circuit and two inverters. The glitch suppressing apparatus uses the specific connection relations and functions of the above components to filter positive glitches and negative glitches in the same circuit, so that the glitch suppressing apparatus can be implemented on a smaller chip area.

Abstract: Driving methods for display panels are provided, in which a Kth row of pixels in a pixel array is driven during a first period, and a K+1th row of pixels in the pixel array is driven during a second period. A control clock applied for a charge pump is toggled at least N times during a third period between the first and second periods, and the control clock is maintained at a fixed logic level during the first and second periods, in which N?2.

Abstract: An electrostatic discharge (ESD) protection circuit is provided. The circuit includes at least one fuse cell and a metal oxide semiconductor field effect transistor (MOSFET). Each of the fuse cells includes a fuse and outputs a bit data according to whether the fuse is melted or not. The MOSFET has a first terminal coupled to each of the fuse cells and a second terminal coupled to a voltage source. The MOSFET is for absorbing an ESD pulse so that the ESD pulse won't melt any one of the fuses.

Abstract: An operating frequency generating method and circuit for a switching voltage converter are provided. The method includes the following steps. First, a reference clock signal and a digital period signal are received. The phase of the digital period signal is delayed according to at least one different delay time, so as to generate at least one delay period signal. The digital period signal or one of the delay period signals is selected as an operating frequency of the switching voltage converter at every predetermined time interval.

Abstract: An image processing method and a related image display system. A video signal with original data items of original dots is received, all the original dots constructing one line of an image. The original data items are processed to perform a zoom function and generate processed data items, which are then written to the memory units of a buffer. Before all the processed data items are written to the memory units, the processed data items stored in the memory units are sequentially read to drive corresponding dots in a line on a display. The time when all the processed data items stored in memory units have been read ends at substantially the same time as that when all the processed data items have been written to memory units.

Abstract: A gamma voltage generator generating a plurality of gamma voltages transformed into a plurality of data signals by a processing unit is disclosed. The processing unit outputs the data signals according to a color separation method. The gamma voltage generator comprises a setting unit, a resistor string, and a selection unit. The setting unit provides a first parameter, a second parameter, and a third parameter. The resistor string generates the gamma voltages according to the first, second, or third parameter. The selection unit is coupled between the setting unit and the resistor string for outputting the first, second, or third parameter to the resistor string according to a control signal group.