Abstract: A built-in-self-test (BIST) circuit for RAMBUS DRAM is disclosed. Unlike other conventional memory devices, a RAMBUS DRAM operates at a much higher speed (e.g., 400 MHz) with a complicated protocol imposed on its input stimuli. In order to provide at-speed testing, a new BIST architecture is needed. The new architecture consists of three major components—two interacting finite state machines (FSMs) and a high-speed time-division multiplexer. The two finite state machines, defining the underlying test algorithms jointly, are used to generate a sequence of generic memory commands. Through the time-division multiplexer, each memory command is then further mapped into a multi-cycle packet compliant to the specification of a target RAMBUS DRAM. Among these components, the finite state machines often form the performance bottleneck. A simple master-slave synchronization mechanism is used to convert these two finite state machines into a multi-cycle path component, thereby eliminating the timing criticality.

Abstract: A transistor structure fabricated on a thin silicon-on-insulator layer. The transistor comprises: a body formed in a silicon layer of a first dopant type; a gate structure formed atop the body; a source adjacent a first edge of the gate structure formed of the first dopant type; and a drain adjacent a second edge of the gate structure formed of the first dopant type.

Abstract: The present invention discloses a novel damascene local interconnect process to avoid junction leakage caused by poor interface of the interconnection with isolation edges. The process comprises the steps of: (a) forming a first dielectric layer over the substrate surface; (b) forming an interconnection in the upper level of the dielectric layer which spans over the first and second active areas; (c) forming a second dielectric layer over the first dielectric layer and the interconnection; (d) etching first and second contact holes adjacent to the opposite ends of the interconnection through the second and first dielectric layers, the first and second contact holes extending down to the first and second active area respectively; and (e) filling the first and second contact holes with first and second conductive plugs respectively, wherein the interconnection thereby connects the first and second conductive plugs to couple the first and second active areas.

Abstract: The present invention discloses a method for forming a self-aligned contact hole, which provides a large process window and ensures full utilization of bottom contact area even when the overlay is not well aligned.

Abstract: A method and system for analyzing the stepping of a reticle mask. A reticle mask includes a first and second corner mask for blocking exposure of a first rectangular area on the wafer surface, a third corner mask for blocking exposure of a second rectangular area on the wafer surface, wherein the first rectangular area is larger than the second rectangular area, and a fourth corner mask of the reticle mask for allowing exposure of a third rectangular area that is smaller than the second rectangular area. A metrology machine produces alignment adjustment values of the result of stepping the reticle mask over the wafer's surface according to reticle mask overlapped exposed corners. The alignment adjustment values comprise an x and y value, and a rotation value. The alignment adjustment values are determined from the difference between the centers of the overlapping results of the third and fourth corner mask.

Abstract: A method for forming a planar structure on a semiconductor substrate is disclosed. The method comprises the steps of: forming an interlayer dielectric atop said substrate; patterning and etching said interlayer dielectric, stopping at said substrate, to form a contact opening; forming a barrier metal layer on the bottom and sidewalls of said contact opening and atop said interlayer dielectric; depositing a conducting layer into said contact opening and atop said barrier metal layer; removing a portion of said conducting layer atop said barrier metal layer, leaving a plug in said contact opening; removing a portion of said barrier layer atop said interlayer dielectric; forming a cap barrier layer on exposed portions of said plug, said barrier metal layer, and said interlayer dielectric; and removing a portion of said cap barrier layer atop said plug.

Abstract: A new one-transistor EEPROM cell structure using a spacer of ferro-electric material (e.g. PZT or BST). The spacer's polarization can be alterable and is used as the storage element of digital information. This new cell offers small cell size, low voltage operation, high endurance, fast write operation, and full function EEPROM compared to conventional EEPROM or F-RAMS.

Abstract: A flash memory cell formed in a semiconductor substrate is disclosed. The cell includes a deep n-well formed within the substrate. Next, a p-well is formed within the deep n-well and a n+ drain region is formed within the p-well. A floating gate is formed above the p-well being separated from the substrate by a thin oxide layer. The floating gate is formed adjacent to the n+ drain region. Finally, a control gate is formed above the floating gate, the floating gate and the control gate being separated by a dielectric layer. The new cell is read by measuring the GIDL current at n+/p-well junction, which is exponentially modulated by the floating gate potential (or its net charge). The new cell is programmed by substrate hot electron injection and is erased by F-N tunneling through the overlap area of floating gate and p-well.

Abstract: A method of making a capacitor over a contact. The method comprises the steps of: (a) depositing an oxide layer over said contact; (b) forming a dual damascene opening in said oxide layer over said contact; (c) depositing a layer of insitu doped polysilicon over said dual damascene opening and said oxide layer; (d) depositing a layer of undoped amorphous polysilicon over said layer of insitu doped polysilicon; (e) removing said layer of undoped amorphous polysilicon and said layer of insitu doped polysilicon that is outside of said dual damascene opening; (f) removing said oxide layer to leave a dual damascene structure comprising insitu doped polysilicon and undoped amorphous polysilicon; (g) forming hemispherical grain (HSG) polysilicon on the surface of said dual damascene structure; (h) forming a dielectric layer over said dual damascene structure; and (i) forming a top electrode over said dielectric layer.

Abstract: A method for manufacturing a self-aligned stacked storage node DRAM cell on a substrate for a capacitor over bit line (COB) process is disclosed.

Abstract: A thin silicon dioxide layer is formed on a substrate to act as a pad oxide layer. Subsequently, a Si.sub.3 N.sub.4 or BN layer is deposited on the pad oxide layer. An in situ doped polysilicon layer is deposited on the Si.sub.3 N.sub.4 or BN layer. A trench is formed in the substrate. An oxide liner is formed along the walls of the trench and on the surface of the in situ doped polysilicon layer. A CVD oxide layer is formed on the oxide liner and refilled into the trench. A two-step chemical mechanical polishing (CMP) removes the layers to the surface of the Si.sub.3 N.sub.4 or BN layer. The first step of the two-step CMP is an oxide slurry CMP that is stopped at about 100 to 500 angstroms from the in situ doped polysilicon layer. The second step of the two-step CMP is a poly slurry CMP that is controlled to stop at the surface of the Si.sub.3 N.sub.4 or BN layer.

Abstract: A method for making a MOSFET in a semiconductor substrate with self aligned source and drain contacts. The method comprises forming a gate oxide layer on the substrate followed by forming a polysilicon gate on the gate oxide layer. A liner oxide layer is formed on the gate and the gate oxide layer and nitride sidewall spacers are formed on the liner oxide layer and adjacent the sidewalls of the gate. A portion of the liner oxide layer and gate oxide layer that lies between the sidewalls of the gate and the nitride sidewall spacers is removed. An oxide layer is then formed around the gate. Next, source and drain regions are formed in the substrate adjacent to the sidewalls of the gate. Finally, a source contact and a drain contact is formed in the area between the gate and the nitride sidewall spacers.

Abstract: A flash memory cell formed on a semiconductor substrate is disclosed. The cell comprises: a p-well formed in the substrate; a gate structure formed atop the p-well, the gate structure including a control gate and a floating gate, the floating gate electrically isolated from the control gate and the semiconductor substrate by a thin dielectric layer; an n- base formed adjacent to a first edge of the gate structure and extending underneath the gate structure; a p+ structure formed within the n- base and adjacent to the first edge of the gate structure; and a n+ structure adjacent a second edge of the gate structure. With such a structure, it is possible to program the cell by band-to-band tunneling enhanced hot electrons generated at the p+ surface. The erase is performed by Fowler-Nordheim tunneling through the n- base region.

Abstract: A method of forming a capacitor for a DRAM memory cell is disclosed. The method comprises the steps of forming a crown shaped capacitor being partially filled with oxide. Next, nitride spacers and polysilicon spacers are formed on the sides of crown capacitor. The remaining oxide is removed and then the oxide spacers are removed to leave a mushroom shaped bottom storage node. A dielectric is deposited and a top conductive node is deposited to complete the capacitor.

Abstract: A flash memory cell formed in a semiconductor substrate. The memory cell comprises: (a) a gate oxide formed atop said semiconductor substrate, said gate oxide including a thin region and a thick region; (b) a floating gate formed atop said thin region; (c) a control gate formed atop said thick region; (d) a drain region formed under said thin region and within said floating gate; (e) a source region formed under said thick region and outside said control gate; and (f) an insulating dielectric layer between said control gate and said floating gate.

Abstract: A method for manufacturing a fin-trench capacitor is disclosed. The method comprises the steps of: forming a plurality of alternating oxide and nitride layers including a top oxide layer, wherein said nitride layers are sandwiched between said oxide layers; forming a storage node contact opening in said plurality of alternating oxide and nitride layers, stopping at said landing pad; removing a portion of said nitride layers along sidewalls of said contract opening; forming a polysilicon layer over said top oxide layer and conformally along said sidewalls of said contact opening; depositing a photoresist layer into said contact opening; removing a portion of said polysilicon layer on top of said top oxide layer; forming a dielectric layer over said top oxide layer and conformally on top of said polysilicon layer along said sidewalls of said contact opening; forming a top conductive layer over said dielectric layer and in said contact opening.

Abstract: A method for forming a metal interconnect structure over a high topography dielectric is disclosed. The method comprises the steps of: depositing a conductive layer over the high topography dielectric layer; depositing a planarized oxide layer over the conducting layer, patterning and etching the planarized oxide layer in accordance with a desired metal interconnect pattern using the conducting layer as an etching stop; using the planarized oxide layer as a hard mask, etching the conducting layer in accordance with the desired metal interconnect pattern imparted onto the planarized oxide layer; and depositing a gap-filling oxide layer over the planarized oxide layer and the high topography dielectric layer.

Abstract: A new method for injecting electrons from a forward biased deep n-well to p-well junction underneath the channel area of a triple-well ETOX cell during substrate hot electron (SHE) programming. The ETOX cell has a control gate, a floating gate, a deep n-well formed in the substrate, a p-well formed in the n-well, a drain implant formed in the p-well, and a source implant formed in the p-well. The method comprises the steps of: forward biasing the deep n-well relative to the p-well; positively biasing the control gate by a voltage sufficient to invert the channel between the source implant and the drain implant; and positively biasing the source and drain. The SHE programming has at least 100 times higher efficiency than channel hot electron (CHE). The cell threshold voltage (V.sub.T) saturates to a value in a self-convergent manner. The SHE can also be used for tightening the Vt spread by a re-programming technique after erase.

Abstract: A multi-level flash memory cell formed in a semiconductor substrate. The memory cell comprises: (a) a deep n-well formed in said semiconductor substrate; (b) a p-well formed within said deep n-well; (c) a first insulating layer formed over said p-well; (d) three floating gates adjacent to and insulated from one another and lying atop said first insulating layer; (e) source and drain regions formed in said p-well and on either side of said three floating gates; (f) a second insulating layer atop said three floating gates and said drain and source regions; and (g) a control gate formed atop said second insulating layer.

Abstract: A method of forming a capacitor for a stacked DRAM memory cell. A contact hole is formed in a dielectric stack of an interlayer dielectric, a first nitride layer, a high temperature oxide (HTO) layer, and a second nitride layer. An in-situ doped amorphous silicon segment is formed in and over the contact hole. The second nitride layer is removed and then a hemispherical grain (HSG) polysilicon layer is formed over the amorphous silicon segment. The HTO layer is removed and a capacitor dielectric layer is formed over the HSG polysilicon layer. Finally, a top conductive layer is formed over the capacitor dielectric layer.