Abstract: A shallow-trench semi-super-junction VDMOS device and a manufacturing method thereof are disclosed. According to an example of the present invention, the shallow-trench semi-super-junction VDMOS device includes: a substrate of a first conduction type; a first epitaxial layer over the substrate; a second epitaxial layer over the first epitaxial layer; two trench regions on both sides of the second epitaxial layer and extending from an upper surface to a bottom of the second epitaxial layer; a third epitaxial layer of a second conduction type formed in each of the trench regions; a fourth epitaxial layer over the second epitaxial layer; and well regions implanted from both sides of the upper surface of the fourth epitaxial layer and connected with the third epitaxial layers in the two trench regions. The present invention gives consideration to the cost of technical process and the convenience of production.