Abstract: Embodiments of ferroelectric memory devices and methods for forming the ferroelectric memory devices are disclosed. In an example, a ferroelectric memory cell includes a first electrode, a second electrode, and a ferroelectric layer disposed between the first electrode and the second electrode. An edge region exposed by the first electrode and the second electrode is covered by at least one of a healing layer or a block layer.

Abstract: Embodiments relate to digital low-dropout (DLDO) with fast feedback and optimized frequency response. Certain embodiments may relate more particularly to ferroelectric memory circuit configurations. For example, a low dropout regulator may include a first circuit path configured to regulate an input voltage to an output voltage at a load, wherein the first path comprises a first transistor. The apparatus may also include a second circuit path configured to feed back an error signal based on the input voltage and the output voltage, wherein the second circuit path comprises an error amplifier.

Abstract: A memory device includes a bit line group having a first bit line and a second bit line. The bit line group includes a first segment, a second segment, and a twist segment conductively connected to the first segment and the second segment. The first segment includes a first portion of the first bit line and a first portion of the second bit line. The second segment includes a second portion of the first bit line and a second portion of the second bit line. The twist segment includes a third portion of the first bit line and a third portion of the second bit line. The first and second portions of the first bit line and the second bit line each extends in a first lateral direction. The third portion of the first bit line is conductively connected to the first and second portions of the first bit line.

Abstract: Embodiments of ferroelectric memory devices and methods for forming the ferroelectric memory devices are disclosed. In an example, a ferroelectric memory cell includes a first electrode, a second electrode, a ferroelectric layer disposed between the first electrode and the second electrode, and a recess between a side surface of at least one of the first electrode or the second electrode and a side surface of the ferroelectric layer.

Abstract: Embodiments of the present disclosure relate to an architecture for random access memory (RAM) circuit configurations. For example, certain embodiments relate to a ferroelectric RAM (FRAM) read only memory (ROM) wordline architecture. A method for power-on reset of a memory can include powering on the memory. The method can also include reading a first flag in a first bit of a first configuration wordline of the memory, wherein the first configuration wordline is one of a plurality of redundant configuration wordlines. The method can further include reading, when the first flag indicates the first configuration wordline is valid, a predetermined number of bytes of the wordline. The method can additionally include configuring operations of the memory based on the predetermined number of bytes, when the first flag indicates the first configuration wordline is valid.

Abstract: Embodiments of a memory, and calibration and operation methods thereof for reading data in memory cells are disclosed. In an example, first data from a plurality of memory cells is sensed, each of the first data corresponding to a first bit. Measurements of first currents converted from voltages of the first data are obtained. Second data from the plurality of memory cells is sensed, each of the second data corresponding to a second bit which is different from the first bit. Measurements of second currents converted from voltages of the second data are obtained. One or more parameters corresponding to one or more components of a charge sharing circuit are adjusted until each of a plurality of reference currents provided by a plurality of transistors is within a predetermined range of a nominal value determined based on the measurements of first currents and the measurements of second currents.

Abstract: Embodiments of a memory, and calibration and operation methods thereof for reading data in memory cells are disclosed. In an example, an apparatus comprises transistors, and a charge sharing circuit coupled to the transistors through gate terminals of the transistors. The charge sharing circuit comprises a programmable electrical source, a first switch coupled to the programmable electrical source, a capacitor coupled to the first switch, and a second switch coupled to the capacitor, the first switch, and the gate terminals of the transistors. The programmable electrical source is configured to provide electrical charges to the capacitor when the first switch is turned on and the second switch is turned off. The capacitor is configured to provide at least a portion of the electrical charges to the gate terminals of the transistors when the first switch is turned off and the second switch is turned on.

Abstract: A wordline driver may include the following: a first transistor having a first node at the input and a second node at an input voltage; a second transistor having a first node at the input node, a second node at a third node of the first transistor, and a third node at ground; a third transistor having a first node at the input voltage, a second node at the first internal node and a third node at a second internal node; a fourth transistor having a first node at an internal node, a second node at a boosted voltage, and a third node at a wordline; a fifth transistor having a first node at an internal node, a second node at the wordline, and a third node at ground; and a sixth transistor between the wordline, the boosted voltage, and the second internal node.

Abstract: Embodiments of operation methods of ferroelectric memory are disclosed. In an example, a method for reading ferroelectric memory cells is disclosed. The ferroelectric memory cells include a first set of ferroelectric memory cells and a second set of ferroelectric memory cells. In a first cycle, first data in a first ferroelectric memory cell of the first set of ferroelectric memory cells is sensed. In a second cycle subsequent to the first cycle, the sensed first data is written back to the first ferroelectric memory cell, and second data in a second ferroelectric memory cell of the second set of ferroelectric memory cells is simultaneously sensed.

Abstract: Embodiments of ferroelectric memory devices and methods for forming the ferroelectric memory devices are disclosed. In an example, a ferroelectric memory cell includes a first electrode, a second electrode, and a ferroelectric layer disposed between the first electrode and the second electrode. An edge region exposed by the first electrode and the second electrode is covered by at least one of a healing layer or a block layer.

Abstract: Embodiments of ferroelectric memory devices and methods for forming the ferroelectric memory devices are disclosed. In an example, a ferroelectric memory cell includes a first electrode, a second electrode, a doped ferroelectric layer disposed between the first electrode and the second electrode. The doped ferroelectric layer includes oxygen and one or more ferroelectric metals. The doped ferroelectric layer further includes a plurality of dopants including at least one dopant from one of Group II elements, Group III elements, or Lanthanide elements. The plurality of dopants are different from the one or more ferroelectric metals.

Abstract: Embodiments of methods for operating ferroelectric memory cells are disclosed. In one example, a method for writing a ferroelectric memory cell is provided. The ferroelectric memory cell includes a transistor and N capacitors. The transistor is electrically connected to a bit line and a word line, respectively, and each of the N capacitors is electrically connected to a respective one of N plate lines in parallel. A plate line signal pulsed between 0 V and Vdd is applied to each of the N plate lines according to a plate line time sequence. A bit line signal pulsed between 0 V and the Vdd is applied to the bit line according to a bit line time sequence to write a valid state of data into the N capacitors. The data consists of N+1 valid states that can be written into the N capacitors. The valid states of the data are determined based on the plate line time sequence. The bit line time sequence is determined based on the valid state of the data written into the N capacitors.

Abstract: Embodiments of three-dimensional (3D) ferroelectric memory devices and methods for forming the ferroelectric memory devices are disclosed. In an example, a 3D ferroelectric memory device includes a substrate and a plurality of ferroelectric memory cells each extending vertically above the substrate. Each of the ferroelectric memory cells includes a capacitor and a transistor electrically connected to the capacitor. The capacitor includes a first electrode, a second electrode, and a ferroelectric layer disposed laterally between the first electrode and the second electrode. The transistor includes a channel structure, a gate conductor, and a gate dielectric layer disposed laterally between the channel structure and the gate conductor.