Abstract: The invention discloses a manufacture method and structure of a power transistor, comprising a lower electrode, a substrate, a drift region, two first conductive regions, two second conductive regions, two gate units, an isolation structure and an upper electrode. The two second conductive region are between the two first conductive regions and the drift region; the two gate units are on the two second conductive regions; the isolation structure covers the two gate units; the upper electrode covers the isolation structure and connects to the two first conductive regions and the two second conductive regions electrically. When the substrate is of the first conductive type, the structure can be used as MOSFET. When the substrate is of the second conductive type, the structure can be used as IGBT. This structure has a small gate electrode area, which leads to less Qg, Qgd and Rdson and improves device performance.

Abstract: This invention discloses a specific superjunction MOSFET structure and its fabrication process. Such structure includes: a drain, a substrate, an EPI, a source, a side-wall isolation structure, a gate, a gate isolation layer and source. There is an isolation layer inside the active area underneath the source. Along the side-wall of this isolation layer, a buffer layer with same doping type as body can be introduced & source can be extended down too to form field plate. Such buffer layer & field plate can make the EPI doping much higher than convention device which results in lower Rdson, better performance, shorter gate so that to reduce both gate charge Qg and gate-to-drain charge Qgd. The process to make such structure is simpler and more cost effective.

Abstract: A vertical complementary field effect transistor (FET) relates to the production technology of semiconductor chips and more particularly to the production technology of power integration circuit. A part of the substrate bottom of the invention extends into the middle layer and form the plug between the two MOS units. There is an output terminal under the substrate layer. When on-state voltage is applied on the gate electrode of the two MOS units, two conduction paths are formed from MOS unit-plug-substrate to the output terminal. This technology can integrate more than two MOS devices. Therefore, the die size is reduced.