Abstract: Method and apparatus are disclosed for cache control in a parallel processing system. The apparatus includes a plurality of application specific engines configured to generate a plurality of commands, a cache array configured to store the plurality of commands, and a cache command controller configured to receive a command asynchronously from an application specific engine in the plurality of application specific engines, update the cache array to include the received command, and validate the updated cache array while maintaining parallel accessing of the cache array by the plurality of application specific engines.

Abstract: Method and system are disclosed for data flow control and dynamic access of task queues in a parallel processing system. The method includes storing tasks to be serviced in a plurality of task queues based on assigned priorities of the tasks, where a task queue in the plurality of task queue stores tasks having assigned priorities in a given priority range, determining a usage rate associated with the each task queue in the plurality of task queues, determining a dynamic access rate corresponding to the each task queue based on the assigned priority level and the usage rate associated with the each task queue in the plurality of task queues, traversing the plurality of task queues in order, and selecting a task queue from the plurality of task queues for service based on the dynamic access rate associated with the task queue.

Abstract: Method and system are disclosed for a programmable state machine controller in a parallel processing system. The programmable state machine controller includes a set of control registers configured to serve a set of application specific engines; a set of task engines configured to access a plurality of application resources in parallel; one or more processors configured to: receive multiple requests from the set of application specific engines, determine availability of the set of task engines and the plurality of application resources being requested, assign the set of task engines to serve the set of application specific engines based on the availability of the set of task engines and the availability of the plurality of application resources being requested, and serve the multiple requests from the set of application specific engines in parallel.

Abstract: Method and system are disclosed for controlling hardware queues. In one embodiment, a system for controlling hardware queues includes a slow memory configured to store a set of hardware queues, a set of fast memories configured to facilitate operations to the set of hardware queues in the slow memory, where a fast memory in the set of fast memories includes a head cache configured to track read operations of a hardware queue in the set of hardware queues, and a tail cache configured to track write operations of the hardware queue in the set of hardware queues, a set of queue control engines configured to control the write operations and read operations to the set of hardware queues through the set of fast memories, and a processor configured to control the set of queue control engines with the write operations and read operations to the set of hardware queues through the set of fast memories.

Abstract: Method and system are disclosed for data flow control in a parallel processing system. The method includes storing tasks to be serviced in a plurality of task queues based on assigned priorities of the tasks, where a task queue in the plurality of task queue stores tasks having assigned priorities in a given priority range, determining a usage rate associated with the each task queue in the plurality of task queues, determining a dynamic access rate corresponding to the each task queue based on the assigned priority level and the usage rate associated with the each task queue in the plurality of task queues, traversing the plurality of task queues in order, and selecting a task queue from the plurality of task queues for service based on the dynamic access rate associated with the task queue.

Abstract: Method and system are disclosed for arbitration of parallel multi-event processing. In one embodiment, a parallel multi-event processing system includes a plurality of hardware components, where each hardware component in the plurality of hardware components is assigned with a unique range of addresses, a plurality of hardware engines, where the plurality of hardware engines are configured to access the plurality of hardware components, a controller configured to perform arbitration on one or more requested transactions among the plurality of hardware engines and the plurality of hardware components based on one or more hardware components in the plurality of hardware components to be accessed, and the plurality of hardware components, the plurality of hardware engines, and the controller are configured to perform the one or more requested transactions according to the arbitration.