Abstract: A method of manufacturing of a semiconductor device, comprising: providing a semiconductor substrate having a first region, a second region and a third region; on the first region, providing a first thin dielectric layer; on the second region, providing a second thick dielectric layer; on the third region, providing an ONO stack; on each of the first, second and third regions, providing at least one gate structure; performing an oxidation step so as to form an oxide layer on each of the gate structures of the first, second and third regions and exposed portions of the first and second dielectric layers; providing a first tetraethyl orthosilicate, TEOS, layer across the second and third regions; blanket depositing a first silicon nitride, SiN, layer across the first, second and third regions; and etching the first SiN layer leaving at least some of said first SiN layer on each gate structure of the first, second and third regions so as to form a first SiN sidewall spacer portion on each gate structure of the f

Abstract: A semiconductor structure for RF applications comprises: a first ?TP GaN transistor on an SOI wafer or die; and a first resistor connected to the gate of said first transistor.

Abstract: A method for forming a low-resistivity tantalum thin film having the following steps: depositing a tantalum layer on a substrate, the tantalum of the layer having a ? phase, treating the deposited tantalum layer by exposure to a radio frequency hydrogen plasma, such that the layer has tantalum in a mixed ?-? phase, at least partially desorbing the hydrogen by carrying out at least one of the following steps: exposure to a radio frequency inert gas plasma, and thermal annealing. The treatment step being configured such that the tantalum layer is subjected to temperatures of less than or equal to 300° C.

Abstract: A method of forming an oxide layer in an in-situ steam generation (ISSG) process, including providing a silicon substrate in a rapid thermal process (RTP) chamber and injecting a gas mixture into the RTP chamber. The method further includes heating a surface of the silicon substrate to a reaction temperature, so that the gas mixture reacts close to the surface to form steam and thereby oxidize the silicon substrate to form the oxide layer on the surface, and wherein the gas mixture comprises hydrogen (H2), oxygen (O2) and nitrous oxide (N2O).

Abstract: A method of forming gate sidewall spacers of two different widths, the method including providing a semiconductor substrate and providing a first and second gate structure on the semiconductor substrate. Each gate structure has at least one sidewall. The method includes blanket depositing, on said first and second gate structures, a first nitride layer and anisotropically etching the first nitride layer leaving at least some of said first nitride layer on at least one sidewall of each gate structure so as to form a first nitride sidewall spacer portion on each gate structure. The method further includes removing the first sidewall spacer portion from the first gate structure, blanket depositing, on said first and second gate structures, a second nitride layer, and anisotropically etching the second nitride layer leaving at least some of said second nitride layer on at least one sidewall of each gate structure so as to form a second nitride sidewall spacer portion on each gate structure.

Abstract: A transistor carried by a substrate comprising an active layer, the transistor comprising: at least one source area and at least one drain area; at least one electrical contact area; at least one conduction channel; at least one gate; wherein the gate comprises: a longitudinal portion; a transverse portion extending on either side of a portion of the active layer and comprising: at least a first portion extending beyond a portion of a first side of the portion of the active layer on a first extension dimension I2; at least a second portion extending beyond a portion of a second side of the portion of the active layer on a second extension dimension I3; and in that: I2>I3 with I3?0.

Abstract: A method for forming an electronic device comprising a first transistor and a second transistor, from a stack of layers comprising an isolating layer surmounted on an active layer made of a semi-conductive material, the method comprising at least the following steps: Forming an isolating trench to define, in the active layer, at least one first active region and at least one second active region, said isolating trench protruding with respect to the active layer of the second active region; Forming a masking layer without covering the active layer of the second active region and without covering a portion of the isolating trench; Etching: of a portion of the thickness of the active layer of the second active region, and of at least one portion of the thickness of said portion of the isolating trench.

Abstract: A method of forming a transistor from a stack of layers comprising at least one insulating layer topped by at least one active layer and at least one first and one second insulating trench defining in the active layer a reception area for receiving the transistor, the transistor comprising a conduction channel formed at least partially in the active layer, the method comprising at least the following steps: forming a grid stack extending over at least the conduction channel; forming a source zone and a drain zone; wherein the formation of the grid stack is carried out in such a way as to provide at least a first and a second portion of the reception zone, not covered by the grid stack.