Abstract: A unit trench capacitor in a substrate includes one or more trenches in the substrate, a dielectric layer, a first electrode and a second electrode. Walls of the one or more trenches are covered by the dielectric layer which separates the first electrode from the second electrode. Each trench follows a closed curve. The closed curve of each trench has one or more elongated parts in directions in which the substrate has a maximum elastic modulus, or the closed curve of each trench has a circular shape if the substrate has an isotropic elastic modulus.

Abstract: An integrated device comprises an electrically conductive substrate having an upper surface comprising a recess and a lower surface for contacting the device, a multi-layer stack provided on the upper surface of the substrate and lining the recess, and an electrically conductive layer for contacting the device provided on the multi-layer stack. The multi-layer stack comprises a first, a second, a third and a fourth dielectric layer. Immediately adjacent dielectric layers have different bandgaps to trap charge carriers at respective interfaces between the dielectric layers during operation of the device.

Abstract: A semiconductor structure for measuring a breakdown voltage of a pn-junction, said semiconductor structure comprises: a substrate; a sensor device comprising an optical active region comprising said pn-junction in said substrate, wherein said sensor device is configured to apply a reverse bias voltage to said pn-junction; and an emitter located adjacent to said optical active region in said substrate and configured to provide charge carriers to said optical active region in order to trigger breakdown of said pn-junction when said reverse bias voltage is equal to or greater than said breakdown voltage.

Abstract: Devices and methods for providing a power transistor structure with a shallow source region include implanting a dopant of a first dopant polarity into a drift region on a source side of a gate structure to form a body region, the body region being self-aligned to, and extending under, the gate structure, and producing a shallow body region wherein the source side hybrid contact mitigates punch through of the shallow self-aligned body region and suppresses triggering of a parasitic bipolar. A retrograde body well, of the first dopant polarity, may be disposed beneath, and noncontiguous with, the shallow self-aligned body region, wherein the retrograde body well improves the electric field profile of the shallow self-aligned body region. A variety of power transistor structures are produced from such devices and methods.

Abstract: A lateral DMOS transistor structure includes a substrate of a first dopant polarity, a body region of the first dopant polarity, a source region, a drift region of a second dopant polarity, a drain region, a channel region, a gate structure over the channel region, a hybrid contact implant, of the second dopant polarity, in the source region, and a respective metal contact on or within each of the source region, gate structure, and drain region. The hybrid contact implant and the metal contact together form a hybrid contact defining first, second, and third electrical junctions. The first junction is a Schottky junction formed vertically between the source metal contact and the body. The second junction is an ohmic junction formed laterally between the source metal contact and the hybrid contact implant. The third junction is a rectifying PN junction between the hybrid contact implant and the channel region.

Abstract: A light sensitive semiconductor structure including a pn-junction in a silicon substrate. The pn-junction includes a central part and an edge part around surrounding the central part, the edge part being in contact with a surface of the silicon substrate. The structure further includes a plasma shielding structure covering at least a depletion width of the pn-junction over at least a part of the edge part where the edge part contacts the surface of the silicon substrate.

Abstract: A dark reference device comprises: a photodiode comprising an optical active area; a light shield configured to prevent light from entering said optical active area, wherein said light shield comprises first and second overlapping metal covers, and wherein each of said metal covers comprises a plurality of openings overlapping said optical active area.

Abstract: Devices and methods for providing a power transistor structure with a shallow source region include implanting a dopant of a first dopant polarity into a drift region on a source side of a gate structure to form a body region, the body region being self-aligned to, and extending under, the gate structure, and producing a shallow body region wherein the source side hybrid contact mitigates punch through of the shallow self-aligned body region and suppresses triggering of a parasitic bipolar. A retrograde body well, of the first dopant polarity, may be disposed beneath, and noncontiguous with, the shallow self-aligned body region, wherein the retrograde body well improves the electric field profile of the shallow self-aligned body region. A variety of power transistor structures are produced from such devices and methods.

Abstract: Devices and methods for providing a power transistor structure with a shallow source region include implanting a dopant of a first dopant polarity into a drift region on a source side of a gate structure to form a body region, the body region being self-aligned to, and extending under, the gate structure, and producing a shallow body region wherein the source side hybrid contact mitigates punch through of the shallow self-aligned body region and suppresses triggering of a parasitic bipolar. A retrograde body well, of the first dopant polarity, may be disposed beneath, and noncontiguous with, the shallow self-aligned body region, wherein the retrograde body well improves the electric field profile of the shallow self-aligned body region. A variety of power transistor structures are produced from such devices and methods.

Abstract: A lateral DMOS transistor structure includes a substrate of a first dopant polarity, a body region of the first dopant polarity, a source region, a drift region of a second dopant polarity, a drain region, a channel region, a gate structure over the channel region, a hybrid contact implant, of the second dopant polarity, in the source region, and a respective metal contact on or within each of the source region, gate structure, and drain region. The hybrid contact implant and the metal contact together form a hybrid contact defining first, second, and third electrical junctions. The first junction is a Schottky junction formed vertically between the source metal contact and the body. The second junction is an ohmic junction formed laterally between the source metal contact and the hybrid contact implant. The third junction is a rectifying PN junction between the hybrid contact implant and the channel region.

Abstract: Devices and methods for providing a power transistor structure with a shallow source region include implanting a dopant of a first dopant polarity into a drift region on a source side of a gate structure to form a body region, the body region being self-aligned to, and extending under, the gate structure, and producing a shallow body region wherein the source side hybrid contact mitigates punch through of the shallow self-aligned body region and suppresses triggering of a parasitic bipolar. A retrograde body well, of the first dopant polarity, may be disposed beneath, and noncontiguous with, the shallow self-aligned body region, wherein the retrograde body well improves the electric field profile of the shallow self-aligned body region. A variety of power transistor structures are produced from such devices and methods.

Abstract: A semiconductor imaging apparatus including a light detection device in a silicon substrate, an optical filter arranged to filter light incident on the light detection device and including a gap for allowing unfiltered light to reach the silicon substrate, an isolation structure for stopping light generated charge carriers in the silicon substrate from reaching the light detection device, and a photodiode for detecting the charge carriers.

Abstract: A light sensitive semiconductor structure including a pn-junction in a silicon substrate. The pn-junction includes a central part and an edge part around surrounding the central part, the edge part being in contact with a surface of the silicon substrate. The structure further includes a plasma shielding structure covering at least a depletion width of the pn-junction over at least a part of the edge part where the edge part contacts the surface of the silicon substrate.

Abstract: A lateral DMOS transistor structure includes a substrate of a first dopant polarity, a body region of the first dopant polarity, a source region, a drift region of a second dopant polarity, a drain region, a channel region, a gate structure over the channel region, a hybrid contact implant, of the second dopant polarity, in the source region, and a respective metal contact on or within each of the source region, gate structure, and drain region. The hybrid contact implant and the metal contact together form a hybrid contact defining first, second, and third electrical junctions. The first junction is a Schottky junction formed vertically between the source metal contact and the body. The second junction is an ohmic junction formed laterally between the source metal contact and the hybrid contact implant. The third junction is a rectifying PN junction between the hybrid contact implant and the channel region.

Abstract: An optical sensor including an array of photodiodes having a first and a second photodiode, each having an optical active region and a peripheral region. The sensor further includes a metal layer having a plurality of metal wires located in the peripheral regions of the first and second photodiodes, wherein the first photodiode is connected to a first subset of metal wires of the plurality of metal wires and wherein the second photodiode is connected to a second, different subset of metal wires of the plurality of metal wires.

Abstract: The present invention relates to a method for manufacturing a membrane component with a membrane made of a thin film (<1 ?m, thin-film membrane). The membrane component can be used in microelectromechanical systems (MEMS). The invention is intended to provide a method for manufacturing a membrane component, the membrane being manufacturable with high-precision membrane dimensions and a freely selectable membrane geometry. This is achieved by a method comprising . . . providing a semiconductor wafer (100) with a first layer (116), a second layer (118) and a third layer (126). Depositing (12) a first masking layer (112) on the first layer (116), the first masking layer (112) defining a first selectively processable area (114) for determining a geometry of the membrane (M1). Forming (13) a first recess (120) by anisotropic etching (13) of the first layer (116) and removing the first masking layer (112).

Abstract: A semiconductor component is to be manufactured in a more time- and cost-efficient manner. The flexibility of the manufacturing process for the production of the semiconductor device is to be increased. This can be achieved with a semiconductor component (50), including a at least two functional units (2) which are identical to one another and are wired to one another, the identical functional units (2) each comprising at least one gate finger (16), at least one source finger (17) and at least one drain finger (18); the wiring comprising conductor tracks. A first track (26) connects the gate fingers (16) respectively, a second track (27) connects the source fingers (17) respectively, and a third track (28) connects the drain fingers (18) of the at least two same functional units (2) respectively.

Abstract: A lateral DMOS transistor structure includes a substrate of a first dopant polarity, a body region of the first dopant polarity, a source region, a drift region of a second dopant polarity, a drain region, a channel region, a gate structure over the channel region, a hybrid contact implant, of the second dopant polarity, in the source region, and a respective metal contact on or within each of the source region, gate structure, and drain region. The hybrid contact implant and the metal contact together form a hybrid contact defining first, second, and third electrical junctions. The first junction is a Schottky junction formed vertically between the source metal contact and the body. The second junction is an ohmic junction formed laterally between the source metal contact and the hybrid contact implant. The third junction is a rectifying PN junction between the hybrid contact implant and the channel region.

Abstract: A lateral DMOS transistor structure includes a substrate of a first dopant polarity, a body region of the first dopant polarity, a source region, a drift region of a second dopant polarity, a drain region, a channel region, a gate structure over the channel region, a hybrid contact implant, of the second dopant polarity, in the source region, and a respective metal contact on or within each of the source region, gate structure, and drain region. The hybrid contact implant and the metal contact together form a hybrid contact defining first, second, and third electrical junctions. The first junction is a Schottky junction formed vertically between the source metal contact and the body. The second junction is an ohmic junction formed laterally between the source metal contact and the hybrid contact implant. The third junction is a rectifying PN junction between the hybrid contact implant and the channel region.