Abstract: Disclosed is a data/clock recovery system for use in a high speed networking transceiver units. The data/clock recovery system includes a four phase sampler circuit that is configured to receive a data input waveform and produce output data. A transition detect circuit that is arranged to receive the output data produced by the four phase sampler circuit. The transition detect circuit is configured to determine whether a clock is leading or lagging the data input waveform. A counter for shifting the clock if the clock is determined by the transition detect circuit to either be leading or lagging the data input waveform, such that the shifting is configured to synchronize the clock and the data input waveform. A decoder that receives control signals from the counter, such that the decoder generates a selection signal. The data/clock recovery system further including a multiplexer for selecting four predetermined clock phases in response to the selection signal generated by the decoder.

Abstract: Disclosed are methods and apparatus for processing packet data received from a physical layer. The processing is performed in-line while streaming packets to an upper layer. The method includes loading an instruction set for custom programming the processing of packet data received from the physical layer. Determining a type of packet data received from the physical layer. Identifying a first word location in the packet data based on the contents of the instruction set. Examining the packet data received from the physical layer at the first identified word location. The method further includes storing an element indicative of information contained in the first identified word location into a data structure, and appending the data structure to the packet data before the packet is streamed to the upper layer. The methods and apparatus also have direct applicability to reducing a CPU's work load during transmissions of data over a network.

Abstract: A network communication controller that provides for rapid detection of available buffer capacity and transmission of pause frames as needed to provide flow control is described. The transmission of a pause frame is requested when a reception buffer capacity achieves an almost full condition. Additionally, an almost empty condition can be used to trigger the transmission of another pause frame. In either case, the pause frames are automatically generated and transmitted ahead of other frames that may also be waiting for transmission. Preferably, the network communication controller is an integrated circuit including circuitry for a MAC layer and a MAC control layer. The flow control provided by the invention is particularly suitable for high speed networks, e.g., 1 Gbps Ethernet networks.

Abstract: Disclosed is a media access controller for transferring data along a computer network. The media access controller includes a transmit media access controller that is configured to process out-going packet data received from an upper layer for transmission to a physical layer. A receive media access controller that is configured to process in-coming packet data received from the physical layer for transmission to the upper layer. A transmit multi-packet queue FIFO for receiving the out-going packet data from the upper layer before being passed to the transmit media access controller. A receive multi-packet queue FIFO for receiving the in-coming packet data that is received by the receive media access controller. The media access controller further including a media access controller manager interfacing with the transmit and receive media access controllers. The media access controller manager being responsible for managing the flow of packet data through the transmit and receive multi-packet queue FIFOs.

Abstract: Disclosed is a media access controller configured to communicate with an upper layer and a lower physical layer. The media access controller includes a receive controller for receiving and processing receive data requests from the lower layer and transferring received data to the upper layer. The method includes receiving data from the lower layer and processing the received data through the receive controller. The processor being performed in accordance with a setting of a plurality of control registers associated with the transmit controller. The method further including receiving a control signal for modifying at least one of the plurality of control registers while the data is being processed through the receive controller. Altering the processing of data being processed within the receive controller based on the modification of the at least one of the plurality of control registers associated with the receive controller, and transferring the processed data to the upper layer.