Abstract: A high speed gain stage including regenerative feedback that forces one output high and one output low providing a two-state output. A differential pair of input transistors of a first conductivity type have respective current terminals coupled between a source node and first and second output nodes and have respective control terminals that receive the analog input voltages. A current source provides source current to the source node. The gain stage includes a differential pair of bias transistors of a second conductivity type having respective current terminals coupled between the first and second output nodes and a reference voltage and having respective control terminals coupled to a bias node. A pair of current-driven transistors of the second conductivity type are cross-coupled at the outputs and to a common node to provide the regenerative feedback. Another transistor is coupled between the common node and the reference voltage to increase switching speed.

Abstract: A low voltage to high voltage level translator that is independent of the high supply voltage. The translator includes first and second transistors with current terminals coupled to a first supply voltage and control terminals that are cross-coupled to one of first and second output nodes. The translator includes first and second input stages each having a first current terminal coupled to a second supply voltage, having a second current terminal coupled to one of the first and second output nodes, and having a control terminal coupled to one of first and second input nodes. The translator further includes first and second resistors, each having a first terminal coupled to the second current terminal of one of the first and second transistors and a second terminal coupled to one of the first and second output nodes. The added resistors enable wider voltage translation and avoid conventional configuration issues.

Abstract: A current to current charge pump including two flying capacitors, a capacitor driver, two rectifying inverters, a bypass capacitor coupled between an input node and a control node, a current control transistor circuit coupled between the control node and a reference node, and an output circuit coupled between upper and lower nodes. One of the upper and lower nodes is held at a constant voltage level. A storage capacitor is coupled between the upper and lower nodes. The capacitor driver drives each of the flying capacitors to opposite states between the control and input nodes using a clock signal. The rectifying inverters are cross-coupled between the flying capacitors, and have supply terminals coupled between the upper and lower nodes. The current control transistor circuit develops an input current at the control node based on a reference current. The output transistor circuit develops an output current that follows the input current.

Abstract: A precision, high voltage, low power differential input stage including static and dynamic gate protection is disclosed herein. The differential input stage incorporates the performance of low voltage transistors with the high voltage capability of high voltage transistors. The transistors may be MOSFETs or the like. In addition, gate protection is provided to protect against large DC voltages and AC voltage transitions. The differential input stage includes a pair of input circuits, such as positive and negative input circuits, each including a cascode combination of low and high voltage transistors. In each cascode stage, the low voltage transistor is fabricated with a gate threshold voltage that is as high or higher than that of the high voltage transistors. The low voltage, high threshold transistors in the cascode stages may be configured to match each other. Resistors and capacitors may be provided to protect against excessive input current and voltage.