Abstract: As one aspect of the present disclosure, a memory access device is disclosed. The device comprises: a command manager configured to receive and manage one or more commands from a plurality of cores; a programming engine unit comprising one or more programming engines configured to perform calculations in response to the one or more commands; and a direct memory access (DMA) controller configured to perform at least one of read access and write access to a memory external to the memory access device in response to the one or more commands, wherein the command manager comprises a command memory configured to store the one or more commands, and a slot management unit configured to allocate one or more cores that correspond to the one or more commands, respectively, to the one or more programming engines in sequence.

Abstract: A data processing acceleration apparatus is disclosed. The data processing acceleration apparatus comprises a hardware accelerator, a memory device, and a memory controller configured to control the hardware accelerator and the memory device. And the memory controller includes a plurality of computing units, a first interface configured to communicate with a host processor based on a first protocol, a second interface configured to communicate with the memory device based on a second protocol, and a third interface configured to communicate with the hardware accelerator based on a third protocol.

Abstract: An electronic device includes a host processor, a volatile memory configured to store a plurality of compressed data, and a controller configured to be connected to the host processor and the volatile memory, wherein the controller is configured to generate a deduplication table that stores hash values associated with respective ones of the plurality of compressed data, identify, based on the deduplication table, first compressed data and second compressed data among the plurality of compressed data that correspond to each other, and delete one of the first compressed data and the second compressed data from the volatile memory.

Abstract: It is one object of the present disclosure to provide measures for securing scalability of the queue depth of cache schedulers by utilizing a plurality of cache schedulers. To this end, a cache memory device in accordance with one embodiment of the present disclosure comprises: a request reception unit configured to receive input transactions; a traffic monitoring module configured to monitor traffic of the input transactions; N cache schedulers, wherein N is an integer greater than or equal to 2; a region setting module configured to set N input transaction regions corresponding to each of the N cache schedulers based on the traffic of the input transactions monitored, wherein input transactions are transferred via an input transaction region set in each cache scheduler; and an access execution unit configured to perform cache memory accesses to input transactions scheduled by the N cache schedulers.

Abstract: As one aspect of the present disclosure, an electronic device is disclosed. The electronic device comprises a receiving unit for receiving a command from an external source, a first buffer for storing a first data value, and an operation engine for loading the first data value from the first buffer in response to the command and performing an operation based on a predetermined calculation formula on the loaded first data value, wherein the first data value is at least one of a result data value obtained by the operation engine previously performing an operation based on the predetermined calculation formula or a query data value to be used for an operation based on the predetermined calculation formula.

Abstract: Provided is a method for managing an adaptive cache pool, which is performed by one or more processors, and includes receiving monitoring information on a cache memory divided into a plurality of cache pools, and adjusting a cache region associated with at least one of the plurality of cache pools based on the monitoring information.

Abstract: As one aspect of the present disclosure, a byte-addressable device is disclosed. The device may include: a volatile memory device; and a controller configured to be connected with a host processor, the volatile memory device, and a non-volatile storage device, wherein the controller may be further configured to communicate with the volatile memory device and the non-volatile storage device based on address information included in a request received from the host processor.

Abstract: As one aspect of the present disclosure, an electronic device is disclosed. The device may include: a volatile memory device; and a controller configured to be connected with a host processor and the volatile memory device, wherein the controller may be further configured to receive a swap-out request for first data in pages from the host processor, generate first compressed data by compressing the first data in response to the swap-out request, and store the first compressed data in the volatile memory device.