Abstract: A method and a processing system for a communications network, including receiving a program code including multiple instructions for the communications network dividing the program into multiple sequences, defining multiple relocation objects, each corresponding to a dependency relationship between two or more of the sequences, and allocating the sequences to a processor instruction memory.

Abstract: The present invention relates to a method and apparatus for pipelined processing of data packets. A pipeline in a processor comprises an access point providing simultaneous access to one or more devices, said devices mainly for data processing operations not provided by the pipeline. The access point comprises at least one FIFO store for storing data entering the access point, a response FIFO store for storing responses received from the device(s), and a synchronization mechanism adapted to synchronize the fetching of the first entry in the FIFO store(s) and the first entry in the response FIFO store. The synchronization mechanism could advantageously be a fixed time delay mechanism. When the fixed time initiated by the fixed time delay mechanism has elapsed, the first response in the response FIFO store is merged into the data stored in the first entry in the FIFO store(s) for storing data entering the access point.

Abstract: A method in a processor is presented, in which data is processed in a pipelined manner, the data being included in a plurality of contexts, comprising a first (3), in addition to which a plurality of operations is adapted to be executed on the contexts. The method comprises executing an initial operation step (6a) of a first operation on the first context (3), and subsequently commencing an execution of an initial operation step (7a) of a second operation on the first context before an execution on the first context (3) of a following operation step (6b) of the first operation is completed.

Abstract: The invention presents a method for a processor (1), and a processor comprising a processing pipeline (2) and at least one interface (3) for data packets. The method is characterized by giving a second data packet (D2) admittance to the pipeline (2) in dependence on cost information (c1), dependent upon an expected time period of residence of a first data packet (D1) in at least a part (P1, . . . , PK) of the pipeline (2). The first data packet (D1) can be identical with the second data packet, but preferably, the first data packet (D1) enters the pipeline (2) before the second data packet (D2).

Abstract: Method in a pipeline processing stage in a processor, includes the steps of: receiving a first block from a first register and a first execution parameter associated with the first block from a second register, the execution parameter having a first value; inspecting a set of data being at least a part of the first block; and, if the set of data differs from a predetermined condition, storing a second execution parameter on a third register and a third execution parameter on the second register, where the second execution parameter has a second value and is associated with the first block and the third execution parameter has the first value and will be associated with a second block. The invention also relates to the pipeline processor, a module, an integrated circuit and a computer unit.

Abstract: Apparatus (3) for processing pipelined data, comprises a storage unit and at least one logic unit (11) for executing operations on a block (4) of data. The storage means comprises an instruction table (12a) comprising at least one instruction, and the at least one logic unit (11) is in at least one pipelined processing stage adapted to receive the block (4) and a first instruction (13a) of the at least one instruction and execute the first instruction (13a). The invention also relates to a method for processing pipelined data, a module (1) for processing pipelined data, an integrated circuit (15), a circuit board assembly (16), a computer unit (22) and a pipelined processing system.