Abstract: A burst access memory comprises a memory array comprising a plurality of memory macros comprising an array of memory cells in rows and columns. The memory cells in each column are connected by at least one local bit line. The array of memory cells and local bit lines define the memory macro. A plurality of global bit lines are each connectable to several corresponding local bit lines. A controller schedules a burst access of the burst access memory by generating a plurality of macro accesses to the memory macros. The plurality of macro accesses are scheduled to start with a predefined delay in relation to each other. Each macro access is divided into a plurality of ordered sub-operations. Consecutive macro accesses are directed to different memory macros and different columns. Data for consecutive macro accesses are arranged in the different memory macros and columns to match the consecutive macro accesses.

Abstract: A burst access memory comprises a memory array comprising a plurality of memory macros comprising an array of memory cells in rows and columns. The memory cells in each column are connected by at least one local bit line. The array of memory cells and local bit lines define the memory macro. A plurality of global bit lines are each connectable to several corresponding local bit lines. A controller schedules a burst access of the burst access memory by generating a plurality of macro accesses to the memory macros. The plurality of macro accesses are scheduled to start with a predefined delay in relation to each other. Each macro access is divided into a plurality of ordered sub-operations. Consecutive macro accesses are directed to different memory macros and different columns. Data for consecutive macro accesses are arranged in the different memory macros and columns to match the consecutive macro accesses.

Abstract: The present disclosure relates to a precharge circuitry for bit lines of an array of memory cells, the precharge circuitry comprising a precharge and limiting unit configured to precharge a first bit line and a second bit line, the precharge and limiting unit further configured to limit a first bit line precharge level of the first bit line and a second bit line precharge level of the second bit line during a precharge cycle of a read and/or write operation of any of the memory cells, wherein the precharge and limiting unit is configured to limit the first bit line precharge level and the second bit line precharge level in a single precharge cycle, preferably without substantial delay.

Abstract: A computer-implemented method for implementing integrated circuit with at least one RAM includes: defining memory portions of the RAM and obtaining memory portions; for each memory portion, generating a memory cell array block corresponding to the sizes of the memory portions, instances of the memory cell array blocks are inferred into a description of the integrated circuit in a hardware description language; for each block, generating timing and physical models; synthesizing description of circuit in the language, including peripheral logic for the blocks, to schematic representation of circuit elements; placing circuit elements, including blocks and peripheral logic, on circuit and routing wires between circuit elements taking into account the timing and physical models of blocks.

Abstract: The present invention relates generally to the field of semiconductor memories and in particular to memory cells comprising a static random access memory (SRAM) bitcell (100). Leakage current in the read path is reduced by connecting a read access transistor terminal either to GND or VDD during read access or write access and idle state. The SRAM cell inverters may be asymmetrical in size. The memory may comprise various boost circuits to allow low voltage operation or application of distinguished supply voltages.

Abstract: The present invention relates generally to the field of semiconductor memories and in particular to memory cells comprising a static random access memory (SRAM) bitcell (100). Leakage current in the read path is reduced by connecting a read access transistor terminal either to GND or VDD during read access or write access and idle state. The SRAM cell inverters may be asymmetrical in size. The memory may comprise various boost circuits to allow low voltage operation or application of distinguished supply voltages.

Abstract: The present invention relates generally to the field of semiconductor memories and in particular to memory cells comprising a static random access memory (SRAM) bitcell (100). Leakage current in the read path is reduced by connecting a read access transistor terminal either to GND or VDD during read access or write access and idle state. The SKAM cell inverters may be asymmetrical in size. The memory may comp rise various boost circuits to allow low voltage operation or application of distinguished supply voltages.

Abstract: The present invention relates generally to the field of semiconductor memories and in particular to memory cells comprising a static random access memory (SRAM) bitcell (100). Leakage current in the read path is reduced by connecting a read access transistor terminal either to GND or VDD during read access or write access and idle state. The SKAM cell inverters may be asymmetrical in size. The memory may comp rise various boost circuits to allow low voltage operation or application of distinguished supply voltages.