Abstract: A computer based media, method and system for developing at least one context frame that summarizes a measure performance situation for one or more levels of one or more organizations, providing applications for managing the measure performance that adapt to the performance situation by using a context frame and a database that automatically captures and incorporates any changes in the measure performance situation.

Abstract: The performance and ease of management of wireless communications environments is improved by a mechanism that enables access points (APs) to perform automatic channel selection. A wireless network can therefore include multiple APs, each of which will automatically choose a channel such that channel usage is optimized. Furthermore, APs can perform automatic power adjustment so that multiple APs can operate on the same channel while minimizing interference with each other. Wireless stations are load balanced across APs so that user bandwidth is optimized. A movement detection scheme provides seamless roaming of stations between APs.

Abstract: The performance and ease of management of wireless communications environments is improved by a mechanism that enables access points (APs) to perform automatic channel selection. A wireless network can therefore include multiple APs, each of which will automatically choose a channel such that channel usage is optimized. Furthermore, APs can perform automatic power adjustment so that multiple APs can operate on the same channel while minimizing interference with each other. Wireless stations are load balanced across APs so that user bandwidth is optimized. A movement detection scheme provides seamless roaming of stations between APs.

Abstract: A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a second electrode interconnection region overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform is used as an edge termination of an epitaxial layer to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions.

Abstract: In a package process of backside illumination image sensor, a wafer including a plurality of pads is provided. A first carrier is processed to form a plurality of blind vias therein. The first carrier is adhered to the wafer so that the blind vias face to the pads correspondingly. A spacing layer is formed and a plurality of sensing components are disposed. A second carrier is adhered on the spacing layer. Subsequently, a carrier thinning process is performed so that the blind vias become the through holes. An insulating layer is formed on the first carrier. An electrically conductive layer is formed on the insulating layer and filled in the though holes to electrically connect to the pads. The package process can achieve the exact alignment of the through holes and the pads, thereby increasing the package efficiency and improving the package quality.

Abstract: In a liquid crystal display (LCD) device having a thin film transistor (TFT), the TFT includes a source electrode, a drain electrode and a semiconductor layer. At least one of the source electrode and drain electrode includes a first layer including copper and a second layer forming an oxide layer and covering the first layer. The semiconductor layer has a substantially linear current-voltage relationship with said source electrode or drain electrode including said first and second layers, when a voltage is applied between the semiconductor layer and said source electrode or drain electrode.

Abstract: A variable resistive element comprising a configuration that an area of an electrically contributing region of a variable resistor body is finer than that constrained by an upper electrode or a lower electrode and its manufacturing method are provided. A bump electrode material is formed on a lower electrode arranged on a base substrate. The bump electrode material is contacted to a variable resistor body at a surface different from a contact surface to the lower electrode. The variable resistor body is contacted to an upper electrode at a surface different from a contact surface to the bump electrode material. Thus, a cross point region between the bump electrode material (the variable resistor body) and the upper electrode becomes an electrically contributing region of the variable resistor body, and then an area thereof can be reduced compared with that of the region regarding the conventional variable resistive element.

Abstract: A variable resistive element comprising a configuration that an area of an electrically contributing region of a variable resistor body is finer than that constrained by an upper electrode or a lower electrode and its manufacturing method are provided. A bump electrode material is formed on a lower electrode arranged on a base substrate. The bump electrode material is contacted to a variable resistor body at a surface different from a contact surface to the lower electrode. The variable resistor body is contacted to an upper electrode at a surface different from a contact surface to the bump electrode material. Thus, a cross point region between the bump electrode material (the variable resistor body) and the upper electrode becomes an electrically contributing region of the variable resistor body, and then an area thereof can be reduced compared with that of the region regarding the conventional variable resistive element.

Abstract: A variable resistive element comprising a configuration that an area of an electrically contributing region of a variable resistor body is finer than that constrained by an upper electrode or a lower electrode and its manufacturing method are provided. A bump electrode material is formed on a lower electrode arranged on a base substrate. The bump electrode material is contacted to a variable resistor body at a surface different from a contact surface to the lower electrode. The variable resistor body is contacted to an upper electrode at a surface different from a contact surface to the bump electrode material. Thus, a cross point region between the bump electrode material (the variable resistor body) and the upper electrode becomes an electrically contributing region of the variable resistor body, and then an area thereof can be reduced compared with that of the region regarding the conventional variable resistive element.

Abstract: A nonvolatile semiconductor memory device include: a two terminal structured variable resistive element, wherein resistive characteristics defined by current-voltage characteristics at both ends transit between low and high resistance states stably by applying a voltage satisfying predetermined conditions to the both ends. A transition from the low resistance state to the high resistance state occurs by applying a voltage of a first polarity whose absolute value is at or higher than first threshold voltage, and the reverse transition occurs by applying a voltage of a second polarity whose absolute value is at or higher than a second threshold voltage. A load circuit is connected to the variable resistive element in series having an adjustable load resistance. A voltage generation circuit applies a voltage to both ends of a serial circuit. The variable resistive element can transit between the states by adjusting a resistance of the load circuit.

Abstract: A nonvolatile semiconductor memory device for suppressing a current consumption caused by a transient current because of the potential change of the bit and word lines at the time of shifting between the programming, reading, and erasing actions in a highly integrated memory cell array is provided. A memory cell (1) array comprises two-terminal memory cells each having a variable resistance element whose resistance value reversibly changes by pulse application are arranged in a row and column directions, wherein the memory cells in a row are connected at one end to common word lines (WL1 to WLn), the memory cells in a column are connected at the other end to common bit lines (BL1 to BLm), and a common unselected voltage VWE/2 is applied to both unselected word and bit lines not connected to the selected memory cell during the reading, programming, and erasing actions for the selected memory cell.

Abstract: A method is provided for forming a metal/semiconductor/metal (MSM) back-to-back Schottky diode from a silicon (Si) semiconductor. The method deposits a Si semiconductor layer between a bottom electrode and a top electrode, and forms a MSM diode having a threshold voltage, breakdown voltage, and on/off current ratio. The method is able to modify the threshold voltage, breakdown voltage, and on/off current ratio of the MSM diode in response to controlling the Si semiconductor layer thickness. Generally, both the threshold and breakdown voltage are increased in response to increasing the Si thickness. With respect to the on/off current ratio, there is an optimal thickness. The method is able to form an amorphous Si (a-Si) and polycrystalline Si (polySi) semiconductor layer using either chemical vapor deposition (CVD) or DC sputtering. The Si semiconductor can be doped with a Group V donor material, which decreases the threshold voltage and increases the breakdown voltage.

Abstract: A method and device for using a set of APIs are provided. Some of the functions which used to be performed by software are now accelerated through hardware.