Abstract: A method of compiling a verification system including a logic system design and a test bench for verifying the logic system design includes: receiving a description of the verification system, parsing the description of the verification system using a first parser and a second parser to generate a first intermediate representation (IR) and a second IR, respectively; analyzing the first and second IRs to generate exchange information; optimizing at least one of the first IR or the second IR based on the exchange information; and generating a first implementable code and a second implementable code respectively based on the first and second IRs after the optimization, wherein the first and second IRs are related by a connection point, and the exchange information is associated with the connection point.

Abstract: A method for generating test cases. The test cases are used to test a plurality of functional units of a logic system design during a simulation process of the logic system design. The method includes acquiring a constraint for generating test cases, and generating a first set of test cases according to the constraint. The first set of test cases is used to cover a part of the plurality of functional units. The method further includes performing a test on the logic system design based on the first set of test cases, determining uncovered functional units that are not covered by the test and a current coverage of the test, and, in response to the current coverage failing to satisfy a preset test coverage condition, generating a second set of test cases according to the uncovered functional units.

Abstract: An emulation and simulation acceleration system includes a plurality of processors, wherein each of the plurality of processors is configured to run a separate simulation task in a parallel manner. Each of the plurality of processors includes a local memory for instructions and data, a memory space for saving received data from other processors of the plurality of processors. The system includes a plurality of connection channels between each processor of the plurality of processors, wherein each of the plurality of connection channels is either virtual or physical, and each of the plurality of connection channels extends through computer hardware or memory mapping. The system includes a plurality of system interfaces configured to interface with other systems for expansion to a larger system or to connect with external target system. Each of the plurality of system interfaces contains a virtual interface and a physical interface for connecting with other simulators.

Abstract: A method for tracing an error of a logic system design includes obtaining an assertion failure of a combinational cone of the logic system design, the combinational cone including a plurality of sub-cones; and obtaining machine learning models of the sub-cones. Each sub-cone represents a sub-circuitry of the logic system design and has one or more input signals and an output signal. The assertion failure indicates an actual signal value of the combinational cone at a current clock cycle being different from an expected output value at the current clock cycle. The method also includes: performing backtracing on the sub-cones according to the assertion failure, the machine learning models of the sub-cones, and dynamic backtracing sensitivities corresponding to the sub-cones, to obtain a backtracing result; and outputting one or more target sub-cones as candidate root causes of the assertion failure according to the backtracing result.

Abstract: The present disclosure provides methods and devices for simulating a design, wherein the design comprises a main class with parameters and a plurality of instances of the main class, wherein the plurality of instances comprise a first instance and a second instance. The method includes: determining, by analyzing the design, a plurality of secondary classes associated with instantiating the main class, wherein the plurality of secondary classes are used as the parameters of the main class and comprise a first secondary class corresponding to the first instance and a second secondary class corresponding to the second instance; translating the design to generate a first temporary code associated with the plurality of instances; generating, based on the first temporary code, a plurality of instance machine codes corresponding to the plurality of instances; and simulating the design based on the plurality of instance machine codes.

Abstract: A method for debugging a logic system design including a target module to be debugged. The method includes receiving a first gate-level netlist associated with the logic system design and a second gate-level netlist associated with the target module that are generated based on a description of the logic system design, obtaining runtime information of an input signal of the target module by running the first gate-level netlist, and obtaining runtime information of the target module by running the second gate-level netlist based on the runtime information of the input signal of the target module.

Abstract: A method for dynamically adjusting a root clock frequency of a logic system design on an emulation system comprises: identifying a plurality of signal paths from one of a plurality of signal inputs of the logic system design to one of a plurality of signal outputs of the logic system design, each of the plurality of signal paths having a signal propagation delay; determining a state of an input signal to a target signal input in a current root clock cycle; determining a target signal path based on the state of the target signal input in the current root clock cycle and one or more logic devices along each signal path associated with the target signal input; and determining the root clock frequency based on a longest signal propagation delay of the signal propagation delays of the plurality of signal paths excluding the target signal path.

Abstract: An efficient and cost-effective method for usage of emulation machine is disclosed, in which a new concept and use model called debug station is described. The debug station methodology lets people run emulation using a machine from one vendor, and debug designs using a machine from another vendor, so long as these machines meet certain criteria. The methodology and its associated hardware hence are called a ‘platform neutral debug station.’ The debug station methodology breaks loose usage of emulation machines, where people can choose the best machine for running a design, and the best machine for debugging, and they do not need to be the same. Unlike the past, where people needed to run emulation and debug a design using same emulator from beginning to the end, the mix-and-match method described herein allows users to use emulators in the most efficient way, and often most cost effective too.