Patents Assigned to XiaMen HaiCun IP Technology LLC
  • Configurable computing array comprising three-dimensional writable memory
    Patent number: 10075168
    Abstract: The present invention discloses a configurable computing array comprising three-dimensional writable memory (3D-W). It is a monolithic integrated circuit comprising an array of configurable computing elements, an array of configurable logic elements and an array of configurable interconnects. Each configurable computing element comprises at least a 3D-W array, which stores at least a portion of a look-up table (LUT) for a math function.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: September 11, 2018
    Assignees: XiaMen HaiCun IP Technology LLC
    Inventor: Guobiao Zhang
  • Three-dimensional one-time-programmable memory comprising off-die address/data-translator
    Patent number: 9666300
    Abstract: The present invention discloses a three-dimensional one-time-programmable memory (3D-OTP) comprising an off-die address/data-translator (A/D-translator). It comprises at least a 3D-array die and at least a peripheral-circuit die. At least an A/D-translator of the 3D-OTP arrays is located on the peripheral-circuit die instead of the 3D-array die. The A/D-translator converts at least an address and/or data between logic and physical spaces.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: May 30, 2017
    Assignees: XiaMen HaiCun IP Technology LLC
    Inventors: Guobiao Zhang, HongYu Yu, RangYu Deng, Chen Shen, Bin Yu, XiangDong Lu, JinFeng Kang, XuGuang Wang, DongYun Zhang, ChenChang Zhan
  • Three-Dimensional One-Time-Programmable Memory Comprising Off-Die Address/Data-Translator
    Publication number: 20170047127
    Abstract: The present invention discloses a three-dimensional one-time-programmable memory (3D-OTP) comprising an off-die address/data-translator (A/D-translator). It comprises at least a 3D-array die and at least a peripheral-circuit die. At least an A/D-translator of the 3D-OTP arrays is located on the peripheral-circuit die instead of the 3D-array die. The A/D-translator converts at least an address and/or data between logic and physical spaces.
    Type: Application
    Filed: October 24, 2016
    Publication date: February 16, 2017
    Applicant: XiaMen HaiCun IP Technology LLC
    Inventor: Guobiao ZHANG