Abstract: A display panel includes a driving circuit including N stages of cascaded shift registers, and each shift register includes: a first control part and a second control part; the second control part is configured to at least receive the signal of the second node, the signal of the third node, and a frequency control signal to generate an output signal; one shift register of the cascaded shift registers connected to a display unit in the first region is configured to receive the first frequency control signal, and one shift register of the cascaded shift registers connected to a display unit in the second region is configured to receive the second frequency control signal; a data refresh frequency of the display unit in the first region is F1, and a data refresh frequency in the second region is F2, F1<F2.

Abstract: A driving method includes driving a display panel at a first-frequency driving mode and a second-frequency driving mode. A first frequency of the first-frequency driving mode is lower than a second frequency of the second-frequency driving mode. In the first-frequency driving mode, a frame time includes a scanning section and a corresponding front and rear porch section immediately following the scanning section. The driving method further includes scanning sub-pixels of the display panel in the scanning section of the first-frequency driving mode, where in the front and rear porch section, the sub-pixels of the display panel are not scanned, and front and rear porch sections corresponding to at least part of a plurality of frames in the first-frequency driving mode include at least one compensation section. The method further includes providing a data signal to each data line of a plurality of data lines of the display panel in a compensation section of the at least one compensation section.

Abstract: A display panel and its fabrication method, and a display device are provided in the present disclosure. The display panel includes a substrate, including a display region; a light-emitting diode (LED) array at the display region, where the LED array includes a plurality of LED units arranged in an array; and a pulse-width modulation chip array at the display region, where the pulse-width modulation chip array includes a plurality of pulse-width modulation chips arranged in an array. The plurality of LED units is electrically connected to the plurality of pulse-width modulation chips in a one-to-one correspondence; and a pulse-width modulation chip of the plurality of pulse-width modulation chips is configured to adjust a light-emitting duration of a corresponding LED unit electrically connected thereto.

Abstract: A display panel includes a driving circuit. The driving circuit includes N levels of shift registers cascaded with each other, N?2. A shift register of the N levels of the shift registers includes a third control unit and a fourth control unit. The third control unit is configured to receive the first voltage signal and a second voltage signal and control a signal of a fourth node in response to the signal of the second node and a signal of a third node. The first voltage signal is a high-level signal and the second voltage signal is a low-level signal. The fourth control unit is configured to receive a third voltage signal and a fourth voltage signal and generate an output signal in response to the signal of the first node and the signal of the fourth node and includes a first transistor and a second transistor.

Abstract: Provided is a display panel. The display panel includes multiple scanning lines, a gate driver circuit, and a timing controller. The timing controller is configured to: receive multiple data enable signals, generate a gate control signal, and provide the gate control signal for the gate driver circuit. The gate control signal includes a start signal, a first clock signal and a second clock signal. The multiple data enable signals are only within the active cycle. The timing controller is configured to generate a rising edge and a falling edge of the start signal within a time interval formed by a rising edge and a falling edge of a first data enable signal in the Nth frame cycle.

Abstract: A display panel and a display apparatus are described. In an embodiment, the display panel includes a substrate and a sub-pixel group located at a side of the substrate. In an embodiment, the sub-pixel group includes sub-pixels of at least two different colors and a light-limiting structure. In an embodiment, the sub-pixels share one light-emitting element. In an embodiment, along a direction perpendicular to the substrate, the light-limiting structure overlaps with the light-emitting element and is located at a light exit side of the light-emitting element. In an embodiment, when the display panel displays an image, the sub-pixels in the sub-pixel group are enabled in sequence. In an embodiment, the when one of the sub-pixels is enabled, the light-limiting structure causes light emitted by the light-emitting element to exit only from the enabled sub-pixel.

Abstract: A display panel includes a shift register, a pixel circuit, and a driving circuit. The shift register includes a first control unit, a second control unit, a third control unit, and a fourth control unit. The first control unit is configured to receive an input signal and control a signal of a first node in response to a first clock signal. The second control unit is configured to receive a first voltage signal and control a signal of a second node in response to the input signal and the first clock signal. The third control unit is configured to receive the first voltage signal and a second voltage signal and control a signal of a fourth node in response to the signal of the second node and a signal of a third node.

Abstract: A display panel with a display region and a non-display region includes a base substrate; a device layer, disposed on one side of the base substrate, covering the display region, and including a cathode layer; and an encapsulation part, arranged around the device layer in the non-display region and including a metal pad layer surrounding the cathode layer. The metal pad layer and the cathode layer are separated by a gap. The cathode layer has a first irregularly-shaped edge, including first deformed portions and second deformed portions that are alternately distributed. Each first deformed portion extends convexly in a direction toward the metal pad layer, and each second deformed portion extends concavely in a direction away from the metal pad layer. In an extending direction of the first irregularly-shaped edge, a length of the first deformed portion is less than or equal to a length of the second deformed portion.

Abstract: Provided are an array substrate and a manufacturing method of an array substrate and a display panel and device. The array substrate includes a pixel circuit. The pixel circuit includes a first transistor and a second transistor, the first transistor includes a first active layer, the second transistor includes a second active layer, and the first active layer and the second active layer both include silicon. The array substrate further includes a first-type inorganic layer and a second-type inorganic layer and a first via hole. The first via hole is located above the first active layer and at least penetrates through the second-type inorganic layer. Concentration of hydrogen ions in the first active layer is less than concentration of hydrogen ions in the second active layer.

Abstract: Provided are display panels and display apparatus. The display panel includes a driving array layer including a pixel circuit and a driving circuit configured to provide a control signal to the pixel circuit. The pixel circuit includes a first capacitor and a first transistor including an active layer including silicon. The driving circuit includes a second capacitor and a second transistor including an active layer including oxide semiconductor. In a direction perpendicular to a plane of the display panel, the first capacitor partially overlaps the first transistor, and the second capacitor does not overlap the second transistor; or in a direction perpendicular to a plane of the display panel, an area of a region where the first capacitor overlaps the first transistor is greater than an area of a region where the second capacitor overlaps the second transistor.

Abstract: Provided are display panels and display apparatus. The display panel includes a driving array layer including a pixel circuit and a driving circuit configured to provide a control signal to the pixel circuit. The pixel circuit includes first and third transistors. The driving circuit includes second and fourth transistors. The first to fourth transistors include an active layer including silicon, an active layer including oxide semiconductor, an active layer including oxide semiconductor, and an active layer including silicon. The first and the third transistors are switching transistors of the pixel circuit, |W1/L1-W4/L4|<|W2/L2-W3/L3|; or the first and the third transistors are a driving transistor and a switching transistor of the pixel circuit, respectively, |W1/L1-W4/L4|>5*|W2/L2-W3/L3|; or the first and third transistors are a switching transistor and a driving transistor of the pixel circuit, respectively, 5*|W1/L1-W4/L4|<|W2/L2-W3/L3|.

Abstract: The display panel includes at least one first touch area group and multiple touch wires; the at least one first touch area group includes two rows and N columns of touch electrodes; and each touch wire is electrically connected to a respective one touch electrode. The display panel further includes a first detection circuit and a second detection circuit; and each touch electrode is separately electrically connected to the first detection circuit and the second detection circuit by a respective one touch wire. The touch short-circuit detection stage includes a first detection stage. The detection method includes providing, at the first detection stage, a short-circuit detection signal for a touch electrode in the first touch electrode row by the first detection circuit; and determining, according to a short-circuit feedback signal generated by the second detection circuit, whether adjacent ones of the touch electrodes located in a same column are short-circuited.

Abstract: Provided are a method for driving a display panel, the method comprises a plurality of picture update periods, wherein at least one of the plurality of picture update periods comprises a first data write stage, a second data write stage, and a data retention stage; at least one of the first data write stage precedes at least one of the second data write stage; at the first data write stage, a gate scanning signal is provided for and a first data voltage is written to a pixel unit; at the second data write stage, the gate scanning signal is provided for and a second data voltage is written to the pixel unit, wherein the first data voltage is less than the second data voltage.

Abstract: A display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a data write device, a drive device and a bias adjustment device. The display panel includes a bias adjustment signal line, at least one of a reset signal line or an initialization signal line. At least one side frame of the display panel includes a bias adjustment signal bus, at least one of a reset signal bus or an initialization signal bus. The bias adjustment signal bus and the reset signal bus are disposed in a same layer, in a case where the bias adjustment signal bus is father away from a display region of the display panel than the reset signal bus, the bias adjustment signal bus is electrically connected to a corresponding bias adjustment signal line through a bridge disposed in a different layer from the bias adjustment signal bus.

Abstract: A display panel and a display device are provided. The display panel includes a first display region and a second display region that are arranged adjacent to each other. The second display region is multiplexed as a photosensitive element disposure region. The first display region includes first sub-pixels, and the second display region includes second sub-pixels and third sub-pixels. The display panel also includes a first substrate and a second substrate that are oppositely disposed. The first substrate is provided with a plurality of signal lines, the plurality of signal lines at least include scan lines and data lines, and the scan lines and the data lines are isolated and crossed to define regions where the first sub-pixel, the second sub-pixel, and the third sub-pixel are located. A signal line of the plurality of signal lines in the second display region is made of a transparent conductive material.

Abstract: A display panel and driving method, and a display device are provided. The display panel includes a display region and a border region. The display region includes a plurality of data lines extending along a first direction. The border region includes a data output circuit, having an output end electrically connected to a data line. The data output circuit includes at least one demultiplexer and 2L first-demultiplexers, where L is a positive integer, and L1. Each demultiplexer group includes a plurality of second-demultiplexers. The plurality of second-demultiplexers share a group of clock signal buses, wherein a portion of the plurality of second-demultiplexers are connected with a portion of the group of clock signal buses, and a remaining portion of the plurality of second-demultiplexers are connected with a remaining portion of the group of clock signal buses.

Abstract: A display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a data write device, a drive device, and a bias adjustment device. The drive device includes a drive transistor. The data write device is configured to provide a data signal for the drive device. The bias adjustment device is configured to provide a bias adjustment signal to the drive device. The pixel circuit includes a first light-emitting control device, the first light-emitting control device is connected between a first power supply voltage signal line and the drive device, and the first power supply voltage signal line is configured to provide a high-level signal, or, the pixel circuit includes an initialization device, the initialization device is connected between an initialization signal line and the light-emitting element, and the initialization signal line is configured to provide a low-level signal.

Abstract: Provided are a display panel and a display device. The display panel includes a first liquid crystal panel and a second liquid crystal panel. The first liquid crystal panel includes a first light-shielding layer which includes a plurality of first light-shielding lines and a plurality of second light-shielding lines, and two adjacent first light-shielding lines and two adjacent second light-shielding lines form a first sub-pixel. The second liquid crystal panel includes a second light-shielding layer which includes a plurality of third light-shielding lines and a plurality of fourth light-shielding lines, and two adjacent third light-shielding lines and two adjacent fourth light-shielding lines form a second sub-pixel. At least one of first light-shielding lines, second light-shielding lines, third light-shielding lines, or fourth light-shielding lines extend in a waveform, and at least one of the first liquid crystal panel or the second liquid crystal panel has a two-domain structure.

Abstract: A display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a driving module, a data-writing module, and a compensation module, and a reset module. The driving module includes a driving transistor. The data-writing module is connected to a source of the driving transistor and configured to selectively provide a data signal for the driving transistor. The compensation module is connected between a gate and a drain of the driving transistor. The reset module is connected between the drain of the driving transistor and a reset signal terminal and configured to provide a reset signal for the gate of the driving transistor. The reset module is used as a bias module. An operating process of the pixel circuit includes a reset stage and a bias stage.

Abstract: The present application discloses a pixel structure and a display device. The pixel structure includes a scan line having a branch structure; and a semiconductor pattern intersecting with the scan line and the branch structure. The semiconductor pattern includes: a first channel region disposed below the scan line; a second channel region disposed below the branch structure; and doping regions respectively disposed at two sides of the first channel region and at two sides of the second channel region. Wherein, the width of the second channel region is less than the width of the first channel region. The pixel structure may improve the display performance of the display screen.