Abstract: The invention concerns a controllable current source or “charge pump” (12) in an integrated circuit, comprising two supply terminals (K1, K2) for the application of two supply potentials (V1, V2) as well as an output terminal (Kout) for the delivery of an output current, connected via a first controllable current path (T1) with the first supply terminal (K1), and via a second controllable current path (T2) with the second supply terminal (K2). In order to improve the current source (12) with regard to the quality of the output signal, it is provided according to the invention that the controllable current source (12) furthermore has a replica (T1?, T2?) of the current paths (T1, T2) in their non-controlled state, of which a replica output terminal (Kout?) is connected via a current mirror (T5 to T8) with the output terminal (Kout).

Abstract: The invention pertains to a circuit arrangement (comparator) for the discrete-time comparison of input signals (ip, vrefp) and for making available a pair of complementary output levels (vdd, vss) which corresponds to the result of the comparison on a line pair (P, N), wherein said circuit arrangement comprises a reset circuit (12) for balancing the line potentials during a reset phase, an input circuit (14) for generating a potential difference on the line pair (P, N) in accordance with an input signal difference, a first bistable flip-flop (16) for amplifying the generated potential difference and a second bistable flip-flop (20) that is connected by means of a connecting circuit (18) and serves for additionally amplifying the generated potential difference to the desired complementary output levels.

Abstract: The invention concerns a controllable current source comprising an output terminal for current delivery, which is connected via first and second current paths with first and second supply terminals, wherein the current paths each having a supply side on/off-switchable current control device and an output side current adjustment device. According to the invention, when the current control device is switched off, a predetermined adjustment potential, whose value lies between the two supply potentials, is applied to a node between the current control device and the current adjustment device. In this way, the performance characteristics of the current source are improved, in particular, negative injection and disturbances in the output current can be avoided. When the current source is used in a PLL, the jitter behavior at the output of the VCO is significantly improved.

Abstract: The invention relates to an integrated circuit arrangement with an active filter comprising transconductance stages, each being adjustable by means of a bias current to be supplied, and comprising a tuning device for tuning the filter, which tuning device adjusts the bias currents of the transconductance stages, wherein the tuning device adjusts the bias current of a first transconductance stage, for the purpose of achieving a desired characteristic of this transconductance stage, and adjusts the bias current of at least one further transconductance stage such that the transconductance of this further transconductance stage deviates from the transconductance of the first transconductance stage by a certain value.

Abstract: An integrated circuit arrangement comprising a reference-current source device for providing a reference current (Iin) and comprising a current mirror device for mirroring the reference current (Iin) to an output current (Iout), wherein the current mirror device comprises a first FET (Q1), operated in saturation, whose channel carries the reference current; as well as a second FET (Q2), operated in saturation, whose channel carries the output current, wherein the gate connections of the two FETs (Q1, Q2) are interconnected in order to ensure identical control voltages (Vgs) at these two FETs (Q1, Q2), wherein at a channel connection of the first FET (Q1), a node for generating the reference current (Iin) carried by the channel of this FET is provided from several reference-current components (Iin1, Iin2), wherein the reference-current components are provided at the node by the reference-current source device, and one (Iin2) of the reference-current components (Iin1, Iin2) is carried by way of a resistance ele

Abstract: An inductive element (10) of an integrated circuit, comprising at least one turn (12), which is formed by an integrated elongated track (14) made of a conductive material, wherein the interior margin of the conductive track (14) comprises at least one recess (30). The invention makes it possible in particular to increase the inductivity of the element (10) in a given available space on the substrate of an integrated circuit.

Abstract: An integrated circuit arrangement is provided according to the present invention, including a cascoded current source (10) and an adjusting circuit (20) for adjusting the operating point (Vg1, Vg2, Vx) of the cascoded current source (10) by providing gate potentials (Vg1, Vg2) for current source FETs (Q1, Q2), the adjusting circuit having: a reference stage, formed by a pair of reference FETs (M2, M1), which are supplied with reference currents (Iref1, Iref2) in such a way that the current densities in the reference FETs (M2, M1) differ by a predetermined factor (N2), for providing reference gate potentials (Vgs1, Vgs2) at the gates of the reference FETs (M2, M1); a processing stage, for providing an adjustment potential (Vgt1+V1) on the basis of the predetermined factor (N2), which is equal to the effective control voltage (Vgt1) of the first reference FET (M2) plus a predetermined additional voltage (V1), and an output FET (M9), which is connected on the source side to the adjustment potential (Vgt1&pl

Abstract: The invention pertains to an integrated circuit arrangement, in particular, in accordance with the CMOS technology, with at least one transconductance amplifier (1) in order to generate a current signal (outp, outm) from an input voltage signal (inp-inm), wherein the transconductance amplifier consists of a first transconductance stage (gm1) and a second transconductance stage (gm2) that are connected in parallel, wherein the first transconductance stage (gm1) has a transconductance that is essentially defined by an ohmic resistance and the second transconductance stage (gm2) has an adjustable transconductance that is essentially defined by a transistor arrangement, and wherein the transconductance of the first transconductance stage (gm1) is higher than the transconductance of the second transconductance stage (gm2).

Abstract: The invention relates to a method for operating a comparator (10) and a pre-amplifier (20) of an integrated circuit, which pre-amplifier is connected in series to the comparator, wherein the comparator (10) is operated with clock pulses in order to compare comparator input signals at periodical decision points (t2), wherein the pre-amplifier (20) is operated with clock pulses so as, in amplification phases (t1 to t2) which precede the decision points (t2), to amplify a signal (IN) which has been input to the pre-amplifier, and to provide the amplified signal (OUT) as a comparator input signal, and so as, in reset phases (t0 to t1) which precede the amplification phases (t1 to t2), to reset the amplification (G) to a minimum value. According to the invention, the pre-amplifier (20) is operated such that its amplification (G) during a rise phase within the amplification phase (t1 to t2) rises gradually and uniformly from the minimum value to a maximum value.

Abstract: The invention relates to an amplifier circuit having a circuit input for a circuit input signal (Vin) to be amplified and an amplification zone for amplifying the circuit input signal (Vin). The invention provides that the amplification zone comprises two amplifiers (OPV1, OPV2), each of which is countercoupled, and which the circuit input signal (Vin) is fed in parallel, and the amplifier outputs of which are or can be connected with a circuit output to provide a circuit output signal (Vout), wherein the amplification input zone of one of the two amplifiers (OPV1) is connected with the amplification input zone of the other of the two amplifiers (OPV2) by means of a further amplifier (A), in such manner that signal distortions at the two amplifier outputs (Vout1, Vout2) essentially cancel each other out. The amplifier circuit according to the invention thus provides for particularly power-efficient amplification of the signal.