Abstract: A five transistor memory cell that can be reliably read and written from a single data line. The cell includes two inverters and a pass transistor. The cell read/write circuitry includes an address supply voltage source which is maintained at a first level during write and at a second level during read, selected to reduce read disturbance. The memory cell read circuitry includes a circuit for precharging the cell data line prior to reading. The state of the memory cell is continuously available at output nodes to control other circuitry even during the read operation. Selective doping of the pull-up transistors of the inverters in the memory cell controls the initial state of the memory cell after the memory cell is powered up.

Abstract: A TTL/CMOS compatible input buffer includes an input inverter and a reference voltage generator. In the TTL mode, the reference voltage generator supplies a reference voltage to the source of the P-channel transistor in the inverter having a magnitude which forces the trigger point of the input inverter to assume a preselected value. Typically the preselected value is selected to be 1.4 volts in order to maximize the input noise margins. A second stage input inverter introduces hysteresis to improve the noise immunity of the system. The reference voltage generator includes an operational amplifier connected to a voltage divider network. In the CMOS mode, the reference voltage generator is disabled and a voltage equal to power supply voltage is provided to the input inverter. As a result, the trigger point of input inverter is higher than 1.4 volts which provides a larger input noise margin. The voltage divider network and the operational amplifier are powered down so that no DC power is consumed.

Abstract: A five transistor memory cell that can be reliably read and written from a single data line. The cell includes two inverters and a pass transistor. The cell read/write circuitry includes an address supply voltage source which is maintained at a first level during write and at a second level during read selected to reduce read disturbance. The memory cell read circuitry includes a circuit for precharging the cell data line prior to read. The state of the memory cell is continuously available at output nodes to control other circuitry even during the read operation.