Abstract: A method for imparting to a general purpose (CISC), or reduced instruction set (RISC), type of central processing unit (CPU; microprocessor) the characteristics and performance of an integer arithmetic digital signal processor (DSP) which executes instructions acting upon multiple ("S") data elements in parallel. The method is applicable to all finite mathematical computations wherein product and sum terms (for example) will never overflow "1/S" fraction of total word width. "S" need not be a multiple of two, but the method is most useful when it is, such as in algorithms containing "butterfly" type computations. It may be used to advantage in the implementation of all discrete orthogonal transforms, and may be generalized to any size CPU word (e.g.: 16-bit, 32-bit, 64-bit, etc.) subject only to limits imposed by the range of vector spaces being handled.