Abstract: A server system can include a plurality of servers interconnected by a network. Each server can include a server processor, a socket configured to receive a module, and at least one removable computation module configured for insertion into the socket. Each computation module can include first processing circuits mounted on the computation module and configured to at least decrypt data packets received by the server independent of the server processor and second processing circuits mounted on the computation module and configured to form a virtual switch for switching the data packets.

Abstract: A device can include a server that includes a host processor and at least one hardware acceleration (hwa) module having at least one computing element formed thereon, the at least one computing element including processing circuits configured to execute a plurality of processes, first memory circuits, second memory circuits, and a data transfer fabric configured to enable data transfers between the processing circuits and the first and second memory circuits; wherein the at least one computing element is configured to transfer data to, or receive data from, any of: the processing circuits, the first memory circuits, the second memory circuits, or other computing elements coupled to the data transfer fabric.

Abstract: A packet handling system is disclosed that can include at least one main processor; a plurality of offload processors connected to a memory bus and configured to provide security related services on packets prior to redirection to the main processor; and a virtual switch respectively connected to the main processor and the plurality of offload processors using the memory bus, the virtual switch configured to receive memory read/write data over the memory bus.

Abstract: A method for handling multiple networked applications using a distributed server system is disclosed. The method can include providing at least one main processor and a plurality of offload processors connected to a memory bus; and operating a virtual switch respectively connected to the main processor and the plurality of offload processors using the memory bus, with the virtual switch receiving memory read/write data over the memory bus.

Abstract: A structured data processing system is disclosed that can include a plurality of XIMM modules connected to a memory bus in a first server, with the XIMM modules each respectively having a DMA slave module connected to the memory bus and an arbiter for scheduling tasks, with the XIMM modules providing an in-memory database; and a central processing unit (CPU) in the first server connected to the XIMM modules by the memory bus, with the CPU arranged to process and direct structured queries to the plurality of XIMM modules.

Abstract: A method is disclosed that includes writing data to predetermined physical addresses of a system memory, the data including metadata that identifies a processing type; configuring a processor module to include the predetermined physical addresses, the processor module being physically connected to the memory bus by a memory module connection; and processing the write data according to the processing type with an offload processor mounted on the processor module.

Abstract: A distributed system server system for providing network overlay services is disclosed. The system can include at least two servers; and a plurality of offload processor modules, each having an input-output (IO) port and multiple offload processors, and including at least a first offload processor module configured to receive and process network packets having a logical identifier, and a second offload processor connected directly to the first offload processor through their respective IO ports, and configured to process at least a portion of the packets having the logical identifier, and returning the processed packets through its IO port.

Abstract: A rack server system for a map/reduce data processing is disclosed. The method can include a plurality of servers arranged in a rack, and a plurality of offload processor modules supported on at least two of the servers, each offload processor module having an input-output (IO) port and multiple offload processors, a first offload processor module configured to execute map steps of the map/reduce data processing, and being connected directly to a second offload processor through their respective IO ports to define a midplane switch, wherein the second offload processor module is configured to execute reduce steps of on data provided from the first offload processor module.

Abstract: An inter-rack server system for a packet processing is disclosed. The system can include a plurality of servers arranged into multiple racks a plurality of top of rack (TOR) units connected to the servers, each TOR unit configured to operate as a TOR switch connecting each of the racks to another of the racks, and a plurality of offload processor modules, each offload processor module having an input-output (IO) port and multiple offload processors, wherein a first offload processor module on a first server on a first rack is connected directly to a second offload processor module on a second server on a second rack, with connection provided through respective IO ports.

Abstract: A distributed system server system for a packet processing without top of rack (TOR) units is disclosed. The system can include a plurality of servers, each having at least one host processor, and a plurality of offload processor modules, each offload processor module having an input-output (IO) port and multiple offload processors, wherein a first offload processor module is connected directly to a second offload processor module through respective IO ports, the first and second offload processors configured to provide bidirectional network packet flow between at least the first and second offload processor modules and at least one host processor without TOR units for an inter-server connection.

Abstract: A rack server system for a packet processing is disclosed. The system can include a plurality of servers mountable in a rack; a top of rack (TOR) unit having connections to each of the servers; and a plurality of offload processor modules, each offload processor module having at least one input-output (IO) port and multiple offload processors, including at least a first offload processor module connected directly to a second offload processor module through their respective IO ports.

Abstract: A system can include a host processor connected to memory via a system memory bus; and at least one offload processor module, including at least one offload processor mounted on the offload processor module, and configured to execute operations on data received over the system memory bus, and to output context data to memory, and read context data from the memory, and hardware scheduling logic mounted on the module and configured to control operations of the at least one offload processor.

Abstract: A method for providing network overlay services using a distributed system server system is disclosed. The method can include providing at least two servers, providing bidirectional network packet flow through input-output (IO) ports of at least two offload processor modules, providing a direct connection between the IO ports of the at least two offload processor modules, and processing network packet data corresponding to a bidirectional network packet flow and a logical identifier with at least one of the offload processor modules.

Abstract: A packet handling system is disclosed that can include at least one main processor, a plurality of offload processors connected to a memory bus and configured to provide security related services on packets prior to redirection to the main processor; an arbiter connected to each of the plurality of offload processors, the arbiter capable of scheduling resource priority for instructions or data received from the memory bus; and a virtual switch respectively connected to the main processor and the plurality of offload processors using the memory bus, with the virtual switch capable of receiving memory read/write data over the memory bus, and further directing at least some memory read/write data to the arbiter.

Abstract: A method for handling packets is disclosed. The method can include providing at least one main processor connected to a plurality of offload processors by a memory bus; configuring the offload processors to provide security related services on packets prior to redirection to the main processor; and operating a virtual switch respectively connected to the main processor and the plurality of offload processors using the memory bus, with the virtual switch capable of receiving memory read/write data over the memory bus.

Abstract: A system can include at least one offload processor having a data cache, the offload processor including a slave interface configured to receive write data and provide read data over a memory bus; an offload processor module including context memory and a bus controller connected to the slave interface; and logic coupled to the offload processor and context memory and configured to detect predetermined write operations over the memory bus; wherein the offload processor is configured to execute operations on data received over the memory bus, and to output context data to the context memory, and read context data from the context memory.