Abstract: A switching fabric for a high-speed, high-performance digital traffic switch guarantees a high degree of resource availability and is resource efficient. Each input port associated with the switching fabric is assigned a time slot in a repetitive time cycle. Data cells received on input ports are staggered so that they are transmitted through the switching fabric in conformance with the assigned time slots. The time slot arrangement allows small data units associated with a particular cell, as they are forwarded through the switching fabric, to be converted into larger parallel data units which respect cell boundaries. The time slot arrangement further allows several of such larger data units to be written into an output queue in a single clock cycle. Thus, cell contention is avoided while making efficient use of queue space.

Abstract: A data transfer system efficiently allocates contiguous address spaces in a destination storage area to packets by maintaining a plurality of lists from which different amounts of contiguous address spaces are allocated. List selection is made based on known or presumed packet characteristics. By arranging different lists to supply contiguous address spaces in different amounts based on packet-specific characteristics, over-allocation of address space may be reduced considerably while contiguous address space is guaranteed on a continuous basis.

Abstract: A user authentication service for a communication network authenticates local users before granting them access to personalized sets of network resources. Authentication agents on intelligent edge devices present users of associated end systems with log-in challenges. Information supplied by the users is forwarded to an authentication server for verification. If successfully verified, the authentication server returns to the agents authorized connectivity information and time restrictions for the particular authenticated users. The agents use the information to establish rules for filtering and forwarding network traffic originating from or destined for particular authenticated users during authorized time periods. An enhanced authentication server may be engaged if additional security is desired. The authorized connectivity information preferably includes identifiers of one or more virtual local area networks active in the network.

Abstract: Custom circuitry for an adaptive, RAM-based, hardware routing engine conforms bit selection dynamically to information made available by a self-optimizing data hashing algorithm. Circuitry includes a staggered multiplexor array for selecting bits from only the most distinctive bit positions of an inbound identifier to effectuate associative comparisons at approximately CAM speeds under perfect or near perfect hash conditions. The custom circuitry includes means for monitoring routing performance and instructing a processing element to correct the hashing algorithm when performance has sufficiently deteriorated. The custom circuitry also has an extended recursive look-up capability.

Abstract: Methods for configuring, maintaining connectivity in and utilizing an ATM network. Neighboring switches share topology information and enable links to neighboring switches for tag switching. Point-to-point tagged virtual connections are established between switches on the best and next-best paths learned from topology information. Point-to-multipoint tagged virtual connections are established on the spanning tree path. Multiple tag allocation requests are included in a single message to preserve bandwidth. Next-best paths are established to reduce latency in event of link failure. Forwarding operations may be performed in hardware to reduce latency during message forwarding.

Abstract: A CAM integrated circuit has a stage-implemented CAM cell which operationally separates CAM read operations into distinct stages, including look-up, prioritization and encoding, that execute independently. The staged implementation is achieved by placing registers between operational logic blocks in the CAM cell. The integrated circuit prioritizes inputs received simultaneously on dual input buses to avoid contention.

Abstract: The present invention, generally speaking, uses input buffering and output control to provide a high-speed, high-performance digital traffic switch. Dropped discrete information units (cells) are dropped at the input port, and so will not be transmitted across the switch fabric. This reduces the traffic load on the switch fabric during congested periods, and makes the switch fabric easier to design and expand. Input buffering/output control allows for the use of smaller buffers than output buffered/output control architectures for the same level of "discrete information unit (cell) drop" performance, and scales well to larger systems. Input buffering/output control provides all the information necessary to the output (data flow) controller necessary to implement very precise control algorithms. These algorithms can then administer switch fabric admission polices and contract enforcement fairly across all input ports.