Abstract: The invention constitutes a unique hardware zero overhead interrupt and task change mechanism for the reduction or elimination of interrupt latency and task change processing overhead delays in computer architectures. Without loss of time, the system performs complete task state saving and restoration between one cycle and the next without software intervention. For each Central Processing Unit (1) register, the invention uses one or more auxiliary latches (3, 4) wherein one latch (3, 4) is used as the “running” latch and one of the auxiliary latches is attached to task storage memory. The invention swaps connections between alternate “running” registers and auxiliary registers while transferring other tasks to and from task storage memory (2). The invention provides a task linking system to allow the linking of tasks for the mandatory sequential execution of the linked tasks.

Abstract: A method for the orderly execution of multiple tasks in a data processing system and a circuit for implementing that method include a plurality of task modules which construct bids based upon the order of the task and its priority. The highest priority highest order number tasks are switched to available system execution resources. The system permits the orderly execution of round-robin task sets in an environment of dynamically changing priorities. When a round-robin task set is interrupted, the system is able to return to the round-robin task set after execution of the higher priority task at the exact point the interruption occurred.

Abstract: A method and circuit are provided for converting a digital signal to an analog signal in the form of a pulse width modulated (PWM) pulse (20). The PWM pulse is generated during an output cycle of a pulse generator to form a pulsetrain output of pulses at a fixed frequency whose widths are determined by dynamically changing digital input data. The method includes the steps of dividing the digital data signal into most significant bit (MSB) and least significant bit (LSB) portions. A PWM pulse is initiated at the beginning of an output cycle and continues while the MSB portion counts down in a counter (24). At the same time, the LSB portion of the digital data signal is converted to a precise phase delay signal which is a subcycle of an oscillator controlling the counter. This phase delay signal is generated after the termination of the MSB count, and halts the high period of the PWM pulse during the output cycle. When the output cycle ends, the process is repeated with the next digital signal.

Abstract: An analog to digital convertor includes a pulse width modulated circuit (PWM) responsive to an analog parameter of an analog signal. The PWM circuit generates a pulse having a duty cycle proportional to the analog parameter. A counter generates a plurality of counterpulses during the pulse duty cycle and a sub-cycle pulse generator generates a series of subcycle pulses during each of the counterpulses. A latch circuit latches the state of the subcycle pulse generator at a predetermined time relative to the termination of the PWM pulse and a logic circuit counts the number of counterpulses which are generated during the PWM pulse. A most significant bit number is represented by the number of counter-pulses and a least significant bit number is determined by the state of the subcycle pulses in the latch. These two numbers added together provide a digital number representative of the analog parameter.

Abstract: The invention constitutes a unique hardware zero overhead interrupt and task change system for the reduction or elimination of interrupt latency and task change processing overhead delays in computer architectures. Without loss of time, the system performs complete task state saving and restoration between one cycle and the next without software intervention. For each Central Processing Unit (1) register, the invention uses one or more auxiliary latches (3, 4) wherein one latch (3, 4) is used as the "running" latch and one of the auxiliary latches is attached to task storage memory. The invention swaps connections between alternate "running" registers and auxiliary registers while transferring other tasks to and from task storage memory (2). The invention provides a task linking system to allow the linking of tasks for the mandatory sequential execution of the linked tasks.