Abstract: Examples of the present disclosure disclose a memory system and an operation method thereof and a storage device and an operation method thereof. The memory system includes a memory device and a memory controller, the kth memory blocks in memory planes in the memory device form one super memory block, super memory blocks form one virtual memory block, the mth physical pages coupled with the nth word lines in the memory planes from a same super memory block in the virtual memory block form one virtual physical page, the virtual physical pages from super memory blocks in a same virtual memory block form one strip; and the memory controller is configured to: receive memory data that needs to be written to a strip; generate parity check data of the strip according to the memory data; and send the memory data and the parity check data to the memory device.

Abstract: The present application discloses a memory device, a control method of a memory device, and a memory system, and belongs to the technical field of memory device. The control method includes: a peripheral circuit receiving an erase instruction, and recording a number of the received erase instructions, wherein the erase instruction is to instruct the peripheral circuit to erase one memory block in a memory cell array; and the peripheral circuit, in response to the number of the received erase instructions reaching a number threshold, selecting one memory page in a first memory block of the memory cell array to perform program processing.

Abstract: A three-dimensional (3D) memory device includes a memory array device, a peripheral device, an etch stop layer, and a backside gate line slit. The memory array device includes a frontside and a backside, a plurality of memory strings, and a plurality of word lines in a staircase structure coupled to the plurality of memory strings. The peripheral device is above the frontside of the memory array device. The etch stop layer is between the memory array device and the peripheral device. The backside gate line slit extends through the backside of the memory array device to the etch stop layer. The backside gate line slit includes a conductive gate line layer and an insulating gate line layer. The 3D memory device can increase manufacturing efficiency, increase yield, reduce thermal stress, reduce fluorine contamination, increase an overlay window, and decrease overlay errors.